System level simulation wrapper for hybrid simulation

• US 9,703,900 B1
• Filed: 07/17/2013
• Issued: 07/11/2017
• Est. Priority Date: 07/17/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Dhume, Nikhil A.
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/944,820
• Time in Patent Office: 1,455 Days
• Field of Search: 716106, 716138
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system level simulation wrapper includes a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication. The system also includes a switch coupled to the plurality of port interfaces. The switch is selectively configured to communicate with a Cycle Accurate hardware description language (HDL) model of an intellectual property (IP) block or a system level model of the IP block.

Claims

1. A computing system for simulating a design of a hardware system, the computing system comprising:

a processor; and

memory storing the design, wherein the design comprises;

a system level simulation wrapper, comprising;

a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication;

a Cycle Accurate HDL model of an intellectual property (IP) block;

a system level model of the IP block; and

a switch coupled to the plurality of port interfaces, wherein the switch is selectively configured to communicate with the Cycle Accurate HDL model or the system level model.

2. The computing system of claim 1, wherein the system level simulation wrapper further comprises one or more translation layers coupled between the switch and the system level model of the IP block, for translating information between the plurality of port interfaces and the system level model of the IP block.

3. The computing system of claim 2, wherein the system level model of the IP block comprises a functional model with a functional interface.

4. The computing system of claim 3, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces;

an intermediate level interface layer for communication with the system level interface layer;

a pin accurate interface layer for communication with the intermediate level interface layer; and

a transaction level modeling (TLM) interface layer for communication with the pin accurate interface layer, wherein the TLM interface layer is configured to receive information from and transmit information to the functional interface of the functional model.

5. The computing system of claim 2, wherein the system level model of the IP block comprises a transaction level model with a transaction level model port interface.

6. The computing system of claim 5, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces;

an intermediate level interface layer for communication with the system level interface layer; and

a pin accurate interface layer for communication with the intermediate level interface layer, wherein the pin accurate interface layer is configured to receive information from and transmit information to the transaction level model port interface of the transaction level model.

7. The computing system of claim 2, wherein the system level model of the IP block comprises a pin accurate model with a pin accurate model port interface.

8. The computing system of claim 7, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces; and

an intermediate level interface layer for communication with the system level interface layer, wherein the intermediate level interface layer is configured to receive information from and transmit information to the pin accurate model port interface of the pin accurate model.

9. The computing system of claim 1, wherein the system level model or the Cycle Accurate HDL model is for simulating a system design.

10. The computing system of claim 9, wherein the Cycle Accurate HDL model or the system level model is configured for simulating the system design at a system level.

11. A computing system for simulating a system design of a hardware system, the computing system comprising:

a processor; and

memory storing the system design, wherein the system design comprises;

a bus; and

a system level simulation wrapper, comprising;

a plurality of port interfaces configured to communicate with the bus;

a Cycle Accurate HDL model of an intellectual property (IP) block;

a system level model of the IP block; and

a switch coupled to the plurality of port interfaces, wherein the switch is selectively configured to communicate with the Cycle Accurate HDL model or the system level model; and

one or more additional Cycle Accurate HDL models coupled to the bus.

12. The computing system of claim 11, wherein the system level simulation wrapper further comprises one or more translation layers coupled between the switch and the system level model of the IP block, for translating information between the plurality of port interfaces and the system level model of the IP block.

13. The computing system of claim 12, wherein the system level model of the IP block comprises a functional model with a functional interface.

14. The computing system of claim 13, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces;

an intermediate level interface layer for communication with the system level interface layer;

a pin accurate interface layer for communication with the intermediate level interface layer; and

a transaction level modeling (TLM) interface layer for communication with the pin accurate interface layer, wherein the TLM interface layer is configured to receive information from and transmit information to the functional interface of the functional model.

15. The computing system of claim 12, wherein the system level model of the IP block comprises a transaction level model with a transaction level model port interface.

16. The computing system of claim 15, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces;

an intermediate level interface layer for communication with the system level interface layer; and

a pin accurate interface layer for communication with the intermediate level interface layer, wherein the pin accurate interface layer is configured to receive information from and transmit information to the transaction level model port interface of the transaction level model.

17. The computing system of claim 12, wherein the system level model of the IP block comprises a pin accurate model with a pin accurate model port interface.

18. The computing system of claim 17, wherein the one or more translation layers comprise:

a system level interface layer for communication with the plurality of port interfaces; and

an intermediate level interface layer for communication with the system level interface layer, wherein the intermediate level interface layer is configured to receive information from and transmit information to the pin accurate model port interface of the pin accurate model.

19. The computing system of claim 11, wherein the Cycle Accurate HDL model or the system level model is for system design simulation.

20. The computing system of claim 11, wherein the system level model is configured to communicate with the one or more additional Cycle Accurate HDL models of the IP block.