Sense amplifier with integrating capacitor and methods of operation

• US 9,704,572 B2
• Filed: 03/20/2015
• Issued: 07/11/2017
• Est. Priority Date: 03/20/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Nigam, Anurag, Siau, Chang, Chen, Yingchang
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/663,775
• Publication Number:
  US 20160276023A1
• Time in Patent Office: 844 Days
• Field of Search: 365 72, 365149, 365205, 365206, 365207, 365208
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.

Claims

1. A non-volatile storage system, comprising:

a sense amplifier output selectively coupled to a bit line;

a first capacitor including a first plate coupled to the sense amplifier output and including a second plate;

a second capacitor including a first plate coupled to the sense amplifier output and a second plate selectively coupled to a voltage source;

a first transistor including a gate coupled to the second plate of the first capacitor, the first transistor includes a first terminal and a second terminal, the second terminal is coupled to ground; and

a second transistor including a gate coupled to the second plate of the first capacitor, the second transistor includes a first terminal and a second terminal, the first terminal is coupled to a current source and is selectively coupled to the second plate of the first capacitor and the second plate of the second capacitor, the second terminal of the second transistor is coupled to the first terminal of the first transistor.

2. The non-volatile storage system of claim 1, wherein:

the second plate of the first capacitor is coupled to the current source during a preset phase;

the second plate of the second capacitor is coupled to the voltage source during the preset phase; and

the sense amplifier output is coupled to ground during the preset phase.

3. The non-volatile storage system of claim 2, wherein:

the second plate of the first capacitor is disconnected from the current source during a sense phase;

the second plate of the second capacitor is disconnected from the voltage source during the sense phase; and

the sense amplifier output is disconnected from ground during the sense phase.

4. The non-volatile storage system of claim 3, wherein:

the second plate of the first capacitor is precharged to a first voltage from the current source during the preset phase; and

the first voltage is based on a threshold of the first transistor.

5. The non-volatile storage system of claim 4, wherein:

the second plate of the second capacitor is precharged to a level of the voltage source during the preset phase.

6. The non-volatile storage system of claim 5, further comprising:

a sense node coupled to the second plate of the second capacitor, the sense node is precharged to the level of the voltage source during the preset phase;

the second capacitor integrates a selected bit line current during the sense phase; and

the sense node is discharged during the sense phase from the level of the voltage source based on an integrated selected bit line current.

7. The non-volatile storage system of claim 6, wherein:

the second plate of the first capacitor is held at the first voltage during the sense phase; and

the sense amplifier output is held at zero volts during the sense phase.

8. The non-volatile storage system of claim 1, further comprising:

a monolithic three-dimensional non-volatile memory array including the bit line.

9. A non-volatile storage system, comprising:

a sense amplifier output connectable to a bit line;

a first capacitor including a first plate coupled to the sense amplifier output and including a second plate;

a second capacitor including a first plate coupled to the sense amplifier output and a second plate;

a first transistor including a gate coupled to the second plate of the first capacitor, the first transistor includes a first terminal and a second terminal, the second terminal is coupled to ground;

a second transistor including a gate coupled to the second plate of the first capacitor, the second transistor includes a first terminal and a second terminal;

a current source coupled to the first terminal of the second transistor;

a first switch coupled between the current source and the second plate of the first capacitor;

a second switch coupled to the second plate of the second capacitor;

a voltage source coupled to the second switch; and

a third switch coupled between the second plate of the second capacitor and the first terminal of the second transistor.

10. The non-volatile storage system of claim 9, wherein:

the first switch couples the current source to the second plate of the first capacitor during a preset phase;

the second switch couples the voltage source to the second plate of the second capacitor during the preset phase; and

the third switch disconnects the second plate of the second capacitor from the first terminal of the second transistor during the present phase.

11. The non-volatile storage system of claim 10, wherein:

the first switch disconnects the current source from the second plate of the first capacitor during a sense phase;

the second switch disconnects the voltage source from the second plate of the second capacitor during the sense phase; and

the third switch couples the second plate of the second capacitor to the first terminal of the second transistor during the sense phase.