Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory

• US 9,704,588 B1
• Filed: 03/14/2016
• Issued: 07/11/2017
• Est. Priority Date: 03/14/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Ray, Biswajit, Chen, Changyuan, Dunga, Mohan
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/069,287
• Time in Patent Office: 484 Days
• Field of Search: 36518501, 36518503, 3651852, 36518524, 36518517, 36518533, 365205, 365208, 365196, 36518906, 36518909, 36518911, 365203
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a verification phase of programming. The preconditioning current can modify a channel resistance to approximate a state during verification to provide a more stable threshold voltage for the memory cells. Preconditioning currents may be applied selectively for select reference levels, select pages, and/or select operations. Selective application of preconditioning currents based on temperature is also provided.

Claims

1. An apparatus, comprising:

a plurality of non-volatile memory cells;

a pre-sense circuit configured to generate a first current in a channel of the non-volatile memory cells for a predefined duration in response to a first sense operation; and

a sense circuit configured to sense based on a cell current of a selected non-volatile memory cell of the plurality after generating the first current in response to the first sense operation, the cell current and the first current are different.

2. The apparatus of claim 1, wherein the pre-sense circuit is configured to generate the first current by:

applying to a bit line connected to the plurality of memory cells a positive bit line voltage;

applying at least one positive word line voltage to a plurality of unselected word lines and a selected word line connected to the selected non-volatile memory cell;

applying to a first select gate and a second select gate at least one positive select voltage; and

applying to a source line of the plurality of memory cells a source line voltage that is less than the positive bit line voltage.

3. The apparatus of claim 1, wherein:

the sense circuit is configured to read the selected non-volatile memory cell by applying a first read reference voltage associated with a first page of data of the selected word line;

the sense circuit is configured to read a second page of data from the selected memory cell after applying the first read reference voltage in association with the first read operation; and

the sense circuit is configured in association with the second page of data to apply a second read reference voltage to the selected word line without the pre-sense circuit generating an associated current in the channel of the non-volatile memory cells.

4. The apparatus of claim 1, further comprising:

a temperature sensor configured to determine a first temperature in association with the first sense operation and a second temperature in association with a second sense operation, the first temperature is below the second temperature;

wherein the pre-sense circuit is configured in response to the first temperature, to generate the first current in the channel of the non-volatile memory cells;

wherein the sense circuit is configured in response to the first temperature, to sense the selected non-volatile memory cell by applying a reference voltage to the selected word line after the pre-sense circuit generates the first current in the channel of the non-volatile memory cells; and

wherein the sense circuit is configured in response to the second temperature, to apply the reference voltage to the selected word line without the pre-sense circuit generating an associated current in the channel of the non-volatile memory cells.

5. The apparatus of claim 1, wherein the predetermined duration is a first predetermined duration, the apparatus further comprising:

a temperature sensor configured to determine a first temperature in association with the first sense operation and a second temperature in association with a second sense operation, the first temperature is below the second temperature;

wherein in response to the first temperature, the pre-sense circuit is configured to provide the first current in the channel for the first pre-determined duration;

wherein in response to the second temperature, the pre-sense circuit is configured to provide the first current in the channel for a second pre-determined duration; and

wherein the first pre-determined duration is longer than the second pre-determined duration.

6. The apparatus of claim 1, further comprising:

a temperature sensor configured to determine a first temperature in association with the first sense operation and a second temperature in association with a second sense operation, the first temperature is below the second temperature;

wherein in response to the second temperature, the pre-sense circuit is configured to generate a second current in the channel of the non-volatile memory cells;

wherein in response to the second temperature, the pre-sense circuit is configured to apply a reference voltage to the selected word line after the pre-sense circuit generates the second current; and

wherein the second current is smaller than the first current.

7. The apparatus of claim 1, wherein:

the sense circuit is configured to read the selected non-volatile memory cell by applying a first read reference voltage to a selected word line connected to the selected non-volatile memory cell after the pre-sense circuit generates the first current;

the sense circuit is configured to read the selected non-volatile memory cell by applying a second read reference voltage after applying the first read reference voltage, the read circuit is configured to apply the second read reference voltage without providing an associated current in the channel.

8. The apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are part of a non-volatile memory array; and

the non-volatile memory array is arranged in a three dimensional structure.

9. The apparatus of claim 1, wherein sensing based on the cell current comprises sensing a voltage based on the cell current.

10. An apparatus, comprising:

a plurality of non-volatile memory cells;

a current generation circuit configured to generate at least a first preconditioning current through the plurality of non-volatile memory cells in association with a first sense operation prior to initiating the first sense operation; and

a read circuit configured to apply a reference voltage to a selected non-volatile memory cell to execute the first sense operation by sensing based on a cell current of the selected non-volatile memory cell after the current generation circuit generates the at least a first preconditioning current, the cell current and the at least a first preconditioning current are different.

11. The apparatus of claim 10, further comprising:

a source line coupled to a first select gate for the plurality of memory cells;

a bit line coupled to a second select gate for the plurality of memory cells; and

a plurality of word lines coupled to the plurality of memory cells;

wherein the current generation circuit is configured to generate the at least a first preconditioning current by applying to the bit line a positive bit line voltage, applying to the plurality of word lines at least one positive word line voltage, applying to the first select gate and the second select gate at least one positive select gate voltage, and applying to the source line of the plurality of memory cells a source line voltage that is less than the positive bit line voltage.

12. The apparatus of claim 10, further comprising:

a temperature sensor configured to determine a first temperature in association with the first sense operation and a second temperature in association with a second sense operation;

wherein in response to the first temperature, the current generation circuit is configured to generate the at least a first preconditioning current;

wherein in response to the second temperature, the read circuit is configured to apply the reference voltage to the selected non-volatile memory cell without a preceding associated preconditioning current being generated through the plurality of non-volatile memory cells; and

wherein the second temperature is above the first temperature.

13. The apparatus of claim 11, wherein:

the sense operation is a first read operation;

the reference voltage is part of a first plurality of read reference voltages for a first page of data associated with the selected word line;

the read circuit is configured to perform a second read operation to read a second page of data from the selected word line after the first read operation; and

the read circuit is configured to apply to the selected word line a second plurality of read reference voltages for a second page of data associated with the selected word line without a preceding associated preconditioning current being generated through the plurality of non-volatile memory cells.

14. A method, comprising:

receiving a request to read data from at least one of a group of memory cells;

in response to the read request, applying to a bit line of the group of memory cells a positive bit line voltage while providing a conduction path from the bit line through the group of memory cells, wherein providing the conduction path includes applying a first voltage to a selected non-volatile memory cell of the group;

after applying the positive bit line voltage, applying to the selected non-volatile memory cell at least one of a series of read reference voltages, the at least one read reference voltage is lower than the first voltage; and

determining data for the selected memory cell based on applying the at least one of a series of read reference voltages.

15. The method of claim 14, wherein:

applying to the selected non-volatile memory cell at least one other of the plurality of read reference voltages without applying to the bit line the positive bit line voltage.

16. The method of claim 14, wherein providing the conduction path through the channel of the group of memory cells comprises:

applying to the group of memory cells at least one positive gate voltage; and

applying to a first select gate and a second select gate for the group of memory cells at least one positive select voltage.

17. The method of claim 16, wherein the request to read data is a first request and the positive bit line voltage is a first bit line voltage, the method further comprises:

determining a first temperature in response to the first request;

receiving a second request to read data from the at least one the group of memory cells;

determining a second temperature in response to the second request, the second temperature is higher than the first temperature;

in response to the second temperature, applying to the bit line a second bit line voltage while providing the conduction path through the group of memory cells, the second bit line voltage is less than the first bit line voltage; and

after applying the second bit line voltage, applying to the selected non-volatile memory cell the at least one of the series of read reference voltages.

18. The method of claim 14, further comprising:

in response to the read request, determining a temperature associated with the group of memory cells;

in response to a first temperature, applying the positive bit line voltage for a first time duration; and

in response to a second temperature, applying the positive bit line voltage for a second time duration, the second time duration is less than the first time duration, the second temperature is higher than the first temperature.

19. An apparatus, comprising:

a bit line;

a plurality of word lines;

a group of non-volatile memory cells coupled to the bit line and the plurality of word lines;

means for generating in association with a first read operation at least a first current from the bit line through the group of non-volatile memory cells; and

means for applying to a selected word line at least one of a plurality of read reference voltages in association with the first read operation after generating the at least a first current.

20. The apparatus of claim 19, wherein the plurality of read reference voltages is a first plurality of read reference voltages for a first page of data associated with the selected word line, the apparatus further comprising:

means for performing a second read operation to read a second page of data from the selected word line after the first read operation; and

means for applying to the selected word line a second plurality of read reference voltages for the second page of data without generating a preceding associated current through the group of non-volatile memory cells.