Semiconductor device with leadframe configured to facilitate reduced burr formation

• US 9,704,725 B1
• Filed: 03/06/2012
• Issued: 07/11/2017
• Est. Priority Date: 03/06/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Hyun Jun, Chung, Hyung Kook, Kim, Hong Bae
• Primary Examiner(s): Eskridge, Cory
• Application Number:
  US13/412,848
• Time in Patent Office: 1,953 Days
• Field of Search: 257666, 257669, 257674, 257676, 257692, 257698, 257730
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/4951 : Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor package or device including a uniquely configured leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. The semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the leads being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor device, comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein the first leads include a first segment having a recessed bottom surface that extends to a distal end proximate to a corresponding peripheral edge segment of the die pad, a second segment having a recessed top surface that extends to a corresponding edge of the semiconductor device, and a third segment between the first and second segments of the first leads, wherein the third segments of the first leads have a thickness, and wherein the second segments of the first leads are recessed to a depth from 10% to 90% of the thickness of the third segments of the first leads;

a plurality of second leads segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein the second leads includes a first segment having a recessed bottom surface that extends to a distal end proximate to a corresponding peripheral edge segment of the die pad, a second segment having a recessed bottom surface that extends to a corresponding edge of the semiconductor device, and a third segment between the first and second segments of the second leads, wherein the third segments of the second leads have a thickness, and wherein the second segments of the second leads are recessed to a depth from 10% to 90% of the thickness of the third segments of the second leads, and wherein the third segments of the plurality of second leads have sidewalls that are substantially devoid of recessed surfaces to maximize contact area;

a semiconductor die attached to the die pad and electrically connected to at least some of the first and second leads; and

a package body defining generally planar bottom and side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that at least portions of the first and second leads are exposed in the bottom and side surfaces of the package body and the first segments of the first leads and the first segments of the second leads are encapsulated by the package body;

the first and second leads being configured such that the portions thereof that are exposed in the side surface are arranged at differing relative elevations; and

further comprising at least one tie bar extending from a corner region of the die pad, the at least one tie bar having a recessed bottom surface along its entire length, the recessed bottom surface of the at least one tie bar covered by the package body.

2. The semiconductor device of claim 1 wherein a portion of the die pad is exposed in the bottom surface of the package body, and wherein at least one adjacent pair of first leads is disposed proximate to a corner region of the semiconductor device, and wherein the first segments of the pair of first leads have different shapes.

3. The semiconductor device of claim 1 wherein the die pad has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die pad.

4. The semiconductor device of claim 3 wherein those portions of the second leads which are exposed in the bottom surface of the package body are generally concentrically positioned between the die pad and those portions of the first leads which are exposed in the bottom surface of the package body.

5. The semiconductor device of claim 4 wherein those portions of the second leads of each set which are exposed in the bottom surface of the package body are offset relative to those portions of the first leads of a corresponding set which are exposed in the bottom surface of the package body.

6. The semiconductor device of claim 1 wherein:

each of the first leads defines a generally rectangular outer end which is exposed in the side surface of the package body; and

each of the second leads defines a generally rectangular outer end which is exposed in the side surface of the package body.

7. The semiconductor device of claim 6 wherein:

the outer end of each of the first leads is of a first area; and

the outer end of each of the second leads is of a second area which is less than the first area.

8. The semiconductor device of claim 6 wherein:

the outer end of each of the first leads defines at least four peripheral edge segments;

the outer end of each of the second leads defines at least four peripheral edge segments; and

one of the peripheral edge segments of each the first leads extends in generally coplanar relation to one of the peripheral edge segments of each of the second leads.

9. The semiconductor device of claim 6 wherein:

the package body extends along each of the at least four peripheral edge segments defined by the outer end of each of the second leads; and

the package body extends along only three of the at least four peripheral edge segments defined by the outer end of each of the first leads.

10. A semiconductor device, comprising:

a die pad;

a plurality of first leads that extend at least partially about the die pad in spaced relation thereto, wherein each first lead includes a first segment having a bottom etched surface that extends to a distal end proximate to a peripheral edge segment of the die pad, a second segment having a recessed top surface that extends to a corresponding edge of the semiconductor device, and a third segment between the first and second segments of the first leads, wherein the third segments of the first leads have a thickness, and wherein the second segments of the first leads are recessed to a depth from about 10% to about 90% of the thickness of the third segments of the first leads;

a plurality of second leads that extend at least partially about the die pad in spaced relation thereto, wherein each second lead includes a first segment having a bottom etched surface that extends to a distal end proximate to a peripheral edge segment of the die pad, a second segment having a recessed bottom surface that extends to a corresponding edge of the semiconductor device, and a third segment between the first and second segments of the second leads, wherein the third segments of the second leads have a thickness, and wherein the second segments of the second leads are recessed to a depth from about 10% to about 90% of the thickness of the third segments of the second leads, and wherein the third segments of the plurality of second leads have sidewalls that are substantially devoid of recessed surfaces;

a semiconductor die attached to the die pad and electrically connected to at least some of the first and second leads; and

a package body defining a side surface, the package body at least partially encapsulating the first and second leads and the semiconductor die such that at least portions of the first and second leads are exposed in the side surface of the package body, and wherein the package body completely encapsulates the first segment of each first lead and the first segment of each second lead;

the first and second leads being configured such that the portions thereof which are exposed in the side surface are arranged at differing relative elevations; and

wherein a portion of the die pad is exposed in the package body, and wherein at least one adjacent pair of first leads is disposed proximate to a corner region of the semiconductor device, and wherein the first segments of the pair of first leads have different shapes.

11. The semiconductor device of claim 10 wherein:

each of the first leads defines a generally rectangular outer end which is exposed in the side surface of the package body; and

each of the second leads defines a generally rectangular outer end which is exposed in the side surface of the package body.

12. The semiconductor device of claim 11 wherein:

the outer end of each of the first leads is of a first area; and

the outer end of each of the second leads is of a second area which is less than the first area.

13. The semiconductor device of claim 11 wherein:

the outer end of each of the first leads defines at least four peripheral edge segments;

the outer end of each of the second leads defines at least four peripheral edge segments; and

one of the peripheral edge segments of each the first leads extends in generally coplanar relation to one of the peripheral edge segments of each of the second leads.

14. The semiconductor device of claim 11 wherein:

the package body extends along each of the at least four peripheral edge segments defined by the outer end of each of the second leads; and

the package body extends along only three of the at least four peripheral edge segments defined by the outer end of each of the first leads.

15. The semiconductor device of claim 10 wherein the semiconductor die is electrically connected to at least some of the first and second leads by conductive wires which are covered by the package body, and wherein the semiconductor device further comprises at least one tie bar extending from a corner region of the die pad, the at least one tie bar having a bottom etched surface along its entire length, the bottom etched surface of the at least one tie bar encapsulated by the package body.

16. A semiconductor device, comprising:

a die pad;

a plurality of first leads that extend at least partially about the die pad in spaced relation thereto, wherein each first lead includes a first segment having a bottom etched surface that extends to a distal end proximate to a corresponding peripheral edge segment of the die pad, a second segment having a top etched surface that extends to a corresponding edge of the semiconductor device, and a third segment between the first and second segments of each first lead, and wherein the second segment of each first lead is etched to a depth between about 10% to about 90% of the thickness of the third segment of each first lead, and wherein at least one adjacent pair of first leads is disposed proximate to a corner region of the semiconductor device, and wherein the first segments of the at least one adjacent pair of first leads have different shapes;

a plurality of second leads that extend at least partially about the die pad in spaced relation thereto, wherein each second lead includes a first segment having a bottom etched surface that extends to a distal end proximate to a corresponding peripheral edge segment of the die pad, a second segment having a bottom etched surface that extends to a corresponding peripheral edge of the semiconductor device and a third segment between the first and second segments of each second lead, the third segment having a thickness, and wherein the second segment of each second lead is etched to a depth between about 10% to about 90% of the thickness of the third segment of each second lead, and wherein the first segments of the second leads are substantially confined to end portions of the third segments of the plurality of second leads to maximize contact area of the third segments;

a semiconductor die attached to the die pad and electrically connected to at least some of the first and second leads; and

a package body defining generally planar bottom and side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that at least portions of the first and second leads are exposed in the bottom and side surfaces of the package body, wherein the package body encapsulates the first segments of each first lead and the first segments of each second lead;

the second segments of the first and second leads being configured such that the portions thereof that are exposed in the side surface are arranged at differing relative elevations.

17. The semiconductor device of claim 16 wherein:

each of the first leads defines a generally rectangular outer end which is exposed in the side surface of the package body and is of a first area; and

each of the second leads defines a generally rectangular outer end which is exposed in the side surface of the package body and is of a second area which is less than the first area.

18. The semiconductor device of claim 17 wherein:

the outer end of each of the first leads defines at least four peripheral edge segments;

the outer end of each of the second leads defines at least four peripheral edge segments;

one of the peripheral edge segments of each the first leads extends in generally coplanar relation to one of the peripheral edge segments of each of the second leads;

the package body extends along each of the at least four peripheral edge segments defined by the outer end of each of the second leads; and

the package body extends along only three of the at least four peripheral edge segments defined by the outer end of each of the first leads.