Through substrate vias with improved connections

• US 9,704,783 B2
• Filed: 02/29/2016
• Issued: 07/11/2017
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Ku-Feng, Lin, Jing-Cheng
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US15/056,935
• Publication Number:
  US 20160181179A1
• Time in Patent Office: 498 Days
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Claims

1. A method of manufacturing a device, the method comprising:

forming a dielectric structure comprising a plurality of metallization layers including at least a bottom metallization layer and a top metallization layer, the plurality of metallization layers each formed in a respective one of a plurality of dielectric layers;

forming a passivation layer over the top metallization layer of the dielectric structure;

etching a first opening in the passivation layer and the dielectric structure, wherein the first opening exposes a metal pad disposed in one of the plurality of dielectric layers;

etching a second opening through the passivation layer and the dielectric structure and into a portion of a substrate disposed below the dielectric structure, wherein the etching the first opening and the etching the second opening occur simultaneously;

lining a top surface of the passivation layer and sidewalls and a bottom surface of each of the first opening and the second opening with an insulation layer;

removing portions of the insulation layer along the bottom surface of the first opening to expose the metal pad;

after removing the portions of the insulation layer, forming a diffusion barrier layer over the top surface of the passivation layer and along the sidewalls and the bottom surface of each of the first opening and the second opening; and

simultaneously filling the first opening and the second opening with a conductive material, an uppermost surface of the conductive material extending above an uppermost surface of the passivation layer.

2. The method of claim 1, further comprising grinding a backside of the substrate to expose the conductive material within the second opening.

3. The method of claim 1, further comprising forming a conductive line interconnecting the conductive material within the first opening and the conductive material within the second opening, a bottom surface of the conductive line in contact with horizontal portions of the diffusion barrier layer over the passivation layer.

4. The method of claim 3, wherein the conductive line is formed in a same step as the step of simultaneously filling the first opening and the second opening.

5. The method of claim 1, further comprising:

overfilling the first opening and the second opening with the conductive material; and

planarizing the overfilled conductive material to form a first conductive via in the first opening and a second conductive via in the second opening.

6. The method of claim 5, further comprising:

forming a trench in a dielectric material above the conductive material within the first opening and the conductive material within the second opening;

lining the trench with a barrier material; and

filling the trench with a second conductive material.

7. The method of claim 6, wherein the second conductive material is a same material as the conductive material.

8. The method of claim 1, wherein the first opening has a first width, when viewed in cross section, and the second opening has a second width, when viewed in cross section, and the second width is wider than the first width.

9. The method of claim 8, wherein the first width is preselected and the second width is preselected such that the first opening extends a first depth and the second opening extends a second depth, greater than the first depth during a common etch process.

10. A method of manufacturing a device, the method comprising:

forming an interconnect structure over a substrate, the interconnect structure including a plurality of conductive pads formed in respective dielectric layers of a plurality of dielectric layers;

forming a passivation layer over the interconnect structure;

etching a first opening aligned with a first conductive pad, the first opening having a first width;

simultaneously with etching the first opening, etching a second opening that extends at least partially through the substrate, the second opening have a second width greater than the first width; and

simultaneously forming a first conductive via in the first opening and a second conductive via in the second opening, topmost surfaces of the first conductive via and the second conductive via extending above a topmost surface of the passivation layer.

11. The method of claim 10, wherein the first width and the second width are preselected such that the first opening extends to the first conductive pad at substantially the same time the second opening extends to at least partially through the substrate using the same process parameters.

12. The method of claim 10, wherein simultaneously forming a first conductive via in the first opening and a second conductive via in the second opening includes:

lining the topmost surface of the passivation layer and sidewalls of the first opening and the second opening with an insulating layer;

lining the topmost surface of the passivation layer and the sidewalls of the first opening and the second opening with a diffusion barrier layer; and

filling the lined first opening and the lined second opening with a conductive material to form the first conductive via and the second conductive via, respectively.

13. The method of claim 12, further comprising forming an interconnection between the first conductive via and the second conductive via.

14. The method of claim 13, wherein forming an interconnection comprises:

forming a trench in a dielectric material above the conductive material within the first opening and the conductive material within the second opening;

lining the trench with a barrier material; and

filling the trench with a second conductive material.

15. The method of claim 10, further comprising simultaneously with etching the first opening and the second opening, etching a third opening aligned with a second conductive pad, the second conductive pad being in a different dielectric layer than the first conductive pad, the third opening having a third width less than the first width.

16. The method of claim 10, further comprising:

overfilling the first opening and the second opening with a conductive material; and

planarizing the overfilled conductive material to form the first conductive via in the first opening and the second conductive via in the second opening.

17. A method of manufacturing a device, the method comprising:

forming an interconnect structure over a substrate, the interconnect structure comprising;

a plurality of low-k dielectric layers;

a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, the plurality of metallization layers including a bottom metallization layer and a top metallization layer; and

a dielectric layer over the top metallization layer;

etching a first opening having a first width, the first opening extending from a top surface of the dielectric layer to a bottom surface within the substrate;

simultaneously with etching the first opening, etching a second opening having a second width, the second opening extending from the top surface of the dielectric layer to a first metal pad in a first one of the plurality of metallization layers; and

simultaneously filling the first opening and the second opening with a conductive material to form a through substrate via (TSV) in the first opening and a deep conductive via in the second opening, uppermost surfaces of the TSV and the deep conductive via extending above the top surface of the dielectric layer.

18. The method of claim 17, further comprising, simultaneously with etching the first opening and the second opening, etching a third opening having a third width, the third opening extending from the top surface of the dielectric layer to a second metal pad in a second one of the plurality of metallization layers different from the first one.

19. The method of claim 17, further comprising forming a conductive line interconnecting the TSV and the deep conductive via, wherein forming the conductive line is performed in a same process step as simultaneously filling the first opening and the second opening with the conductive material.

20. The method of claim 17, wherein a ratio of the first width of the first opening to the second width of the second opening is greater than about 1.5.