Three dimensional fully molded power electronics module having a plurality of spacers for high power applications

• US 9,704,819 B1
• Filed: 03/29/2016
• Issued: 07/11/2017
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: Gao, Ziyang, Lv, Ya
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US15/084,442
• Time in Patent Office: 469 Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13294 with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/27334 using preformed layer
• CPC Class Codes: H01L 2224/27849 Reflowing
• CPC Class Codes: H01L 2224/29082 Two-layer arrangements
• CPC Class Codes: H01L 2224/29083 Three-layer arrangements
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29191 : The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
• CPC Class Codes: H01L 2224/29294 : with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/33181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81024 : Applying flux to the bonding area
• CPC Class Codes: H01L 2224/8109 : Vacuum
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83024 : Applying flux to the bonding area
• CPC Class Codes: H01L 2224/8309 : Vacuum
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92242 : the first connecting process involving a layer connector
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin

Abstract

A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.

Claims

1. A power electronic package, comprising:

a first substrate having a patterned inner surface that includes a first conductive region;

a second substrate oppositely disposed from the first substrate and having a patterned inner surface that includes a second conductive region;

a plurality of chips sandwiched between the first substrate and the second substrate and each of the chips having a top surface and a bottom surface;

a first plurality of solder blocks disposed between the top surface of the chips and the first conductive region of the first substrate;

a second plurality of solder blocks disposed between the bottom surface of the chips and the second conductive region of the second substrate; and

at least three spacers each having a first end that contacts the first substrate, a second end that contacts the second substrate, and a height that is based on a height of the chips, on a height of the first plurality of solder blocks, and on a height of the second plurality of solder blocks such that the height variation of the power electronic package is controlled by the spacers;

wherein the first substrate includes a ceramic layer sandwiched between two electrically conductive layers and the second substrate includes a ceramic layer sandwiched between two electrically conductive layers.

2. The power electronic package of claim 1, wherein the height of the spacers is an average of a first total height and a second total height when a difference between the first total height and the second total height is in a range of 0.0 mm to 0.1 mm, wherein the first total height equals a height of a first chip plus a height of the first solder blocks that connect the first chip to the first substrate, and a height of the second solder blocks that connect the first chip to the second substrate, and the second total height equals a height of a second chip plus a height of the first solder blocks that connect the second chip to the first substrate, and a height of the second solder blocks that connect the second chip to the second substrate, wherein the height of the second solder blocks is determined by analyzing thermal properties and reliability performance of the power electronic package.

3. The power electronic package of claim 1, wherein the first plurality of solder blocks are solder balls with a height of 60% to 80% of a width of the solder balls.

4. The power electronic package of claim 1, wherein each of the chips includes a total height that equals the height of the chip plus the heights of the first and second solder blocks, and a difference between the total height of each of the chips is in a range of 0.0 mm to 0.1 mm.

5. The power electronic package of claim 1 further comprising:

a third plurality of solder blocks that contact the first conductive region of the first substrate and contact the second conductive region of the second substrate.

6. The power electronic package of claim 1 further comprising:

a molding compound that encapsulates the power electronic package including the first substrate, the second substrate, and the chips.

7. The power electronic package of claim 1, wherein an outer surface of the first substrate and the second substrate is exposed directly to ambient air.

8. The power electronic package of claim 1, wherein the spacers are formed of silicon and have a cross sectional shape as one of a circle-shape and a polygon-shape.

9. A fully molded power electronic module, comprising:

a first direct bonded copper (DBC) substrate;

a second DBC substrate oppositely disposed from the first DBC substrate;

a plurality of chips sandwiched between the first DBC substrate and the second DBC substrate and each of the chips having a top surface and a bottom surface;

a first plurality of solder blocks disposed between the top surface of the chips and the first DBC substrate;

a second plurality of solder blocks disposed between the bottom surface of the chips and the second DBC substrate; and

four spacers each having a first end that contacts the first DBC substrate, a second end that contacts the second DBC substrate, and a height that is equal to a height of one of the chips plus a height of one of the first plurality of solder blocks plus a height of one of the second plurality of solder blocks such that the spacers divert load from the chips to the spacers.

10. The fully molded power electronic module of claim 9, wherein the first plurality of solder blocks are solder balls with a height of 60% to 80% of a width of the solder balls.

11. The fully molded power electronic module of claim 9, wherein each of the chips includes a total height that equals the height of the chip plus the heights of the first and second solder blocks, and a difference between the total height of each of the chips is in a range 0.0 mm to 0.1 mm.

12. The fully molded power electronic module of claim 9 further comprising:

a third plurality of solder blocks that contact the first DBC substrate and contact the second DBC substrate.

13. The fully molded power electronic module of claim 9, wherein six spacers are spaced around a perimeter of the fully molded power electronic module.

14. The fully molded power electronic module of claim 9, wherein the spacers are positioned adjacent four corners of the fully molded power electronic module.

15. The fully molded power electronic module of claim 9, wherein the spacers are formed of silicon and have a cross sectional shape as one of a circle-shape and a polygon-shape.

16. A method of fabricating a power electronic package, comprising:

providing a first direct bonded copper (DBC) substrate having an electrically non-conductive region and an electrically conductive region;

providing a second DBC substrate having a first solder base that holds a first chip, having a second solder base that holds a second chip, having an electrically non-conductive region and an electrically conductive region;

determining, by analyzing thermal properties and reliability performance of the first and second DBC substrates and the first chip, a thickness of the first solder base and a thickness of a first solder block disposed between the first chip and the first DBC substrate;

calculating a first height by adding the thickness of the first solder base together with a thickness of the first chip and the thickness of the first solder block;

determining, by analyzing thermal properties and reliability performance of the first and second DBC substrates and the second chip, a thickness of the second solder base and a thickness of a second solder block disposed between the second chip and the first DBC substrate;

calculating a second height by adding the thickness of the second solder base together with a thickness of the second chip and the thickness of the second solder block;

determining an optimized height by taking an average of the first height and the second height when a difference between the first height and the second height is less than 0.1 mm; and

mounting, between the first and second DBC substrates, at least three spacers that have a height equal to the optimized height.

17. The method of claim 16, wherein the height of the first solder block is 60% to 80% of a width of the first solder block, and the height of the second solder block is 60% to 80% of a width of the second solder block.

18. The method of claim 16 further comprising:

disposing a third solder block that contacts the electrically conductive region of the first DBC substrate and that contacts the electrically conductive region of the second DBC substrate.

19. The method of claim 16 further comprising:

pressing the first DBC substrate against the second DBC substrate until the spacers contact the electrically non-conductive region of the second DBC substrate.

20. The method of claim 16 further comprising:

flowing an encapsulant to encapsulate the power electronic package.