Semiconductor memory device having an electrically floating body transistor

• US 9,704,869 B2
• Filed: 08/16/2016
• Issued: 07/11/2017
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc., Zeno Semiconductors, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/238,343
• Publication Number:
  US 20160358924A1
• Time in Patent Office: 329 Days
• Field of Search: 365189011, 36518904
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

Claims

1. A semiconductor memory cell formed in a semiconductor, the semiconductor memory cell comprising:

a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and

a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, and the buried region is discontinuous along one direction;

wherein said floating body region stores a charge or lack of charge indicative of a state of the semiconductor memory cell selected from at least first and second states; and

wherein said buried region is configured to generate impact ionization when the semiconductor memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the semiconductor memory cell is in the other of said first and second states.

2. The semiconductor memory cell of claim 1, further comprising a bit line region at said surface, the bit line region having the second conductivity type.

3. The semiconductor memory cell of claim 2, further comprising a single shared contact through which bit line regions of adjacent memory cells are coupled.

4. The semiconductor memory cell of claim 2, further comprising a common region through which bit line regions of adjacent cells are coupled, the common region having the second conductivity type.

5. The semiconductor memory cell of claim 1, further comprising a gate above said surface and insulated from said surface by an insulating layer.

6. The semiconductor memory cell of claim 1, further comprising a first well region of the first conductivity type beneath the buried region.

7. The semiconductor memory cell of claim 1, wherein said buried region is adapted to receive electrical signals of different amplitude or polarity, and wherein said electrical signals depend on an operation of said semiconductor memory cell.

8. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells comprising;

a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

a buried region located beneath the surface of the memory cell, wherein the buried region has a second conductivity type,

wherein the rows of the plurality of memory cells define a first direction and the columns of the plurality of memory cells define a second direction, and said buried region is discontinuous along the first direction or the second direction and commonly connected to at least two of said memory cells,

and when a first memory cell of said plurality of memory cells is in a first state and a second memory cell of said plurality of memory cells is in a second state, application of a bias to said buried region maintains said first memory cell in said first state and said second memory cell in said second state.

9. The array of memory cells of claim 8, wherein each of said memory cells further comprises a bit line region located in the floating body region and substantially exposed at said surface, the bit line region having the second conductivity type.

10. The array of memory cells of claim 9, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said buried regions.

11. The array of memory cells of claim 10, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said bit line regions.

12. The array of memory cells of claim 8, wherein each of said plurality of memory cells further comprises a gate region above said surface and insulated from said surface by an insulating layer.

13. The array of memory cells of claim 8, wherein each of said plurality of memory cells further comprises a first well region of the first conductivity type beneath the buried region.

14. The array of memory cells of claim 8, wherein said buried region is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.

15. The array of memory cells of claim 8, further comprising a voltage generator circuitry configured to apply a voltage to said buried regions.

16. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of said memory cells comprising;

a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

a buried region located beneath the surface of the memory cell, wherein the buried region has a second conductivity type,

wherein said floating body region stores a charge or lack of charge indicative of a state of the semiconductor memory cell selected from at least first and second states; and

wherein the rows of the plurality of memory cells define a first direction and the columns of the plurality of memory cells define a second direction, and said buried region is discontinuous along the first direction or the second direction and commonly connected to at least two of said plurality of memory cells,

wherein said buried region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.

17. The array of memory cells of claim 16, wherein each of said memory cells further comprises a bit line region located in the floating body region and substantially exposed at said surface, the bit line region having the second conductivity type.

18. The array of memory cells of claim 17, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said buried region.

19. The array of memory cells of claim 18, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said bit line region.

20. The array of memory cells of claim 16, wherein said buried region is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.