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Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

  • US 9,704,870 B2
  • Filed: 02/09/2017
  • Issued: 07/11/2017
  • Est. Priority Date: 03/02/2010
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

    a transistor comprising a source region, a floating body region, a drain region, and a gate;

    a first bipolar device having a first floating base region, a first emitter, and a first collector; and

    a second bipolar device having a second floating base region, a second emitter, and a second collector,wherein said first floating base region and said second floating base region are common to said floating body region;

    wherein said first collector is common to said second collector;

    wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell,wherein said transistor is usable to access said memory cell;

    wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; and

    wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string.

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