Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 9,704,870 B2
• Filed: 02/09/2017
• Issued: 07/11/2017
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductors, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/428,921
• Publication Number:
  US 20170154888A1
• Time in Patent Office: 152 Days
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell,

wherein said transistor is usable to access said memory cell;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line; and

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string.

2. The integrated circuit of claim 1, wherein said number of said at least one contact is less than said number of semiconductor memory cells.

3. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in series.

4. The integrated circuit of claim 1, wherein said semiconductor memory cells are connected in parallel.

5. The integrated circuit of claim 1, wherein said integrated circuit is fabricated on a bulk silicon substrate.

6. The integrated circuit of claim 1, wherein said link or string of semiconductor memory cells is formed in a fin structure.

7. The integrated circuit of claim 1, wherein said number of said at least one contact is two.

8. The integrated circuit of claim 1, wherein said gate is insulated from said floating body region.

9. The integrated circuit of claim 1, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

10. The integrated circuit of claim 9, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.

11. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell,

wherein said transistor is usable to access said memory cell;

wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;

wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and

wherein at least one of said at least one control line is connected to a read circuitry.

12. The integrated circuit of claim 11, wherein said number of said at least one contact is less than said number of said semiconductor memory cells.

13. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in series.

14. The integrated circuit of claim 11, wherein said semiconductor memory cells are connected in parallel.

15. The integrated circuit of claim 11, wherein said integrated circuit is fabricated on a bulk silicon substrate.

16. The integrated circuit of claim 11, wherein said link or string of semiconductor memory cells is formed in a fin structure.

17. The integrated circuit of claim 11, wherein said number of said at least one contact is two.

18. The integrated circuit of claim 11, wherein said gate is insulated from said floating body region.

19. The integrated circuit of claim 11, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

20. The integrated circuit of claim 19, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.