Pixel structure having high aperture ratio and circuit

• US 9,704,937 B2
• Filed: 09/19/2014
• Issued: 07/11/2017
• Est. Priority Date: 09/02/2014
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Lo, Changcheng, Li, Wenhui, Tseng, Chihyuan, Hu, Yutong
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US14/426,987
• Publication Number:
  US 20160247869A1
• Time in Patent Office: 1,026 Days
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. A transparent electrode, a pixel electrode and a flat isolation layer sandwiched between the transparent electrode and the pixel electrode construct a transparent capacitor.

Claims

1. A pixel structure having high aperture ratio, comprising a substrate, a first gate electrode and a second gate electrode, located above one region of the substrate;

a gate isolation layer, located on the first gate electrode, the second gate electrode and the substrate, such that the gate isolation layer completely covers the first gate electrode, substantially covers the substrate, and exposes two ends of the second gate electrode;

a first semiconductor layer, located on the gate isolation layer and right over the first gate electrode;

a second semiconductor layer, located on the gate isolation layer and right over the second gate electrode;

an etching stopper layer, located on the first semiconductor layer, the second semiconductor layer and the gate isolation layer;

a first source electrode and a first drain electrode, located on the first semiconductor layer and the etching stopper layer;

a second source electrode and a second drain electrode, located on the second semiconductor layer and the etching stopper layer, such that the first source electrode and first drain electrode are connected to the first semiconductor layer and one of the first source electrode and the first drain electrode is connected to one of the exposed ends of the second gate electrode, and the second source electrode and the second drain are connected to the second semiconductor layer;

a protective layer, located on the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the etching stopper layer;

a transparent electrode, located on the protective layer and above another region of the substrate, such that the transparent electrode is connected to the other one of the two exposed ends of the second gate electrode;

an isolation layer with a flat top surface, located on the protective layer and the transparent electrode;

a pixel electrode, located on the isolation layer with the flat top surface, such that the pixel electrode is connected to one of the second source electrode and the second drain electrode and overlaps with the transparent electrode;

a pixel definition layer, located on the isolation layer with the flat top surface and the pixel electrode, such that the pixel definition layer comprises an opening corresponding to an overlapping district of the pixel electrode and the transparent electrode;

wherein the first gate electrode, a layer of the first source electrode and the first drain electrode, and the etching stopper layer, the first semiconductor layer, and the gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor;

the second gate, a layer of the second source electrode and the second drain electrode, and the etching stopper layer, the second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor; and

the transparent electrode, the pixel electrode and the flat isolation layer sandwiched transparent electrode and the pixel electrode construct a transparent capacitor; and

wherein the transparent capacitor corresponds in position to and located under the opening of the pixel definition layer with the pixel electrode located on the flat top surface of the isolation layer and exposed through the opening and the transparent electrode located under and covered by the isolation layer and connected to the gate electrode of the second thin film transistor.

2. The pixel structure having high aperture ratio according to claim 1, wherein the transparent capacitor constructs an activation area part of the pixel structure.

3. The pixel structure having high aperture ratio according to claim 1, wherein the transparent electrode is an indium tin oxide (ITO) transparent electrode or an indium zinc oxide (IZO) transparent electrode, and the pixel electrode is an ITO pixel electrode or an IZO pixel electrode.

4. The pixel structure having high aperture ratio according to claim 1, further comprising a photoresist spacer located on the pixel definition layer.

5. The pixel structure having high aperture ratio according to claim 1, further comprising a first top gate electrode right over the first gate electrode and located between the protective layer and the isolation layer with the flat top surface, and a second top gate electrode right over the second gate electrode and located between the protective layer and the isolation layer with the flat top surface.

6. The pixel structure having high aperture ratio according to claim 5, wherein the first top gate electrode, the second top gate electrode and the transparent electrode are formed at the same time.

7. The pixel structure having high aperture ratio according to claim 1, wherein the first semiconductor layer is an indium gallium zinc oxide (IGZO) semiconductor layer, and the second semiconductor layer is an IGZO semiconductor layer.