Light-emitting device and manufacturing method thereof

• US 9,705,029 B2
• Filed: 06/26/2013
• Issued: 07/11/2017
• Est. Priority Date: 06/26/2013
• Status: Active Grant

• Current Assignee: Epistar Corporation
• Original Assignee: Epistar Corporation
• Inventors: Huang, Chien-Fu, Chiu, Hsin-Chih, Lu, Chih-Chiang, Lin, Chun-Yu
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US14/901,415
• Publication Number:
  US 20160155894A1
• Time in Patent Office: 1,476 Days
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/02 characterised by the semiconductor bodies
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

The present disclosure provides a method for manufacturing a light-emitting device, comprising: providing a first substrate; providing a semiconductor stack on the first substrate, the semiconductor stack comprising a first conductive type semiconductor layer, a light-emitting layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the light-emitting layer, wherein the semiconductor stack is patterned and comprises a plurality of blocks of semiconductor stack separated from each other, and wherein the plurality of blocks of semiconductor stack comprise a first block of semiconductor stack and a second block of semiconductor stack; performing a separating step to separate the first block of semiconductor stack from the first substrate, and the second block of semiconductor stack remained on the first substrate; providing a permanent substrate comprising a first surface, a second surface, and a third block of semiconductor stack on the first surface; and bonding one of the first block of semiconductor stack and the second block of semiconductor stack to the second surface.

Claims

1. A method for manufacturing a light-emitting device, comprising:

providing a first substrate;

providing a semiconductor stack on the first substrate, the semiconductor stack comprising a first conductive type semiconductor layer, a light-emitting layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the light-emitting layer, wherein the semiconductor stack is patterned and comprises a plurality of blocks of semiconductor stack separated from each other, and wherein the plurality of blocks of semiconductor stack comprise a first block of semiconductor stack and a second block of semiconductor stack;

performing a separating step to separate the first block of semiconductor stack from the first substrate, and the second block of semiconductor stack remained on the first substrate;

providing a permanent substrate comprising a cavity having a first surface which exposes an inner area of the permanent substrate, a second surface, which is non-coplanar with the first surface of the cavity, and a third block of semiconductor stack on the first surface; and

bonding one of the first block of semiconductor stack and the second block of semiconductor stack to the second surface.

2. The method of claim 1, wherein a difference in a dominant wavelength between one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded and the third block of semiconductor stack is greater than or equal to 1 nm.

3. The method of claim 1, wherein a difference in a forward voltage between one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded and the third block of semiconductor stack is greater than or equal to 2%.

4. The method of claim 1, wherein a difference in a luminous intensity between one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded and the third block of semiconductor stack is greater than or equal to 3%.

5. The method of claim 1, wherein the separating step comprises:

forming a first sacrificial layer on the first block of semiconductor stack;

providing a temporary substrate;

bonding the temporary substrate and the first sacrificial layer; and

separating the first block of semiconductor stack from the first substrate.

6. The method of claim 1, further comprising bonding the second block of semiconductor stack to the permanent substrate, the step comprising:

bonding the first substrate and the permanent substrate with alignment so that the second block of semiconductor stack is bonded to the second surface; and

separating the second block of semiconductor stack from the first substrate.

7. The method of claim 1, further comprising bonding the second block of semiconductor stack to the permanent substrate, the bonding step comprising:

providing a temporary substrate;

bonding the second block of semiconductor stack to the temporary substrate;

separating the second block of semiconductor stack from the first substrate;

bonding the temporary substrate and the permanent substrate with alignment so that the second block of semiconductor stack is bonded to the second surface; and

separating the second block of semiconductor stack from the temporary substrate.

8. The method of claim 1, further comprising performing lithography and etching processes to the permanent substrate so that the second surface and the first surface are non-coplanar.

9. The method of claim 1, wherein the third block of semiconductor stack is bonded to the first surface with a first bonding layer, and one of the first block of semiconductor stack and the second block of semiconductor stack on which bonding is performed is bonded to the second surface with a second bonding layer, and wherein the first bonding layer and the second bonding layer have different thicknesses.

10. The method of claim 1, wherein the plurality of blocks of semiconductor stack are classified into being in a first region or a second region, and the first region is substantially a circle, and the second region is substantially an annular shape surrounding the first region.

11. The method of claim 10, wherein one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded is in the first region, and the third block of semiconductor stack is separated from the second region and bonded to the permanent substrate.

12. The method of claim 10, further comprising performing a measuring step to measure an optical characteristic value or an electrical characteristic value of all blocks of semiconductor stack, and determining the first region and the second region based on a predetermined differential value for the optical characteristic value or the electrical characteristic value.

13. The method of claim 10, further comprising obtaining a predetermined value for a radius of the first region through statistics.

14. The method of claim 1, further comprising forming a metal line between one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded and the third block of semiconductor stack to form an electrical connection.

15. The method of claim 14, wherein one of the first block of semiconductor stack and the second block of semiconductor stack on which bonding is performed and the third block of semiconductor stack are electrically connected in series or in parallel.

16. The method of claim 1, wherein the third block of semiconductor stack is separated from a third substrate and bonded to the permanent substrate.

17. The method of claim 1, further comprising classifying the blocks of semiconductor stack into a typical bin group, a low bin group, and a high bin group based on an optical characteristic value or an electrical characteristic value of all blocks of semiconductor stack, wherein the optical characteristic value or the electrical characteristic value in the high bin group is greater than that in the typical bin group, and the optical characteristic value or the electrical characteristic value in the typical bin group is greater than that in the low bin group.

18. The method of claim 17, wherein the third block of semiconductor stack is separated from the first substrate, and one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded is selected from one of the high bin group and the low bin group, and the third block of semiconductor stack is selected from the other.

19. The method of claim 17, wherein the third block of semiconductor stack is separated from the first substrate, and one of the first block of semiconductor stack and the second block of semiconductor stack which is bonded and the third block of semiconductor stack are selected from the typical bin group.

20. The method of claim 1, wherein the plurality of blocks of semiconductor stack comprises the third block of semiconductor stack.