Switch circuit and SPDT switch circuit
First Claim
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1. An SPDT circuit comprising:
- an antenna;
a first MOS transistor group transmitting a transmission signal from a transmitting end to the antenna according to a turn-on operation thereof and blocking introduction of a reception signal received in the antenna into the transmitting end according to a turn-off operation thereof;
a first gate resistor group including gate resistors each connected to gates of the respective transistors of the first MOS transistor group;
a second MOS transistor group applied with gate power complementary to turn-on gate power of the first MOS transistor group to operate complementarily to the first MOS transistor group, transferring the reception signal to a receiving end, and blocking leakage of the transmission signal to the receiving end;
a second gate resistor group including gate resistors each connected to gates of the respective transistors of the second MOS transistor group; and
a variable gate resistor circuit group increasing resistance values of the respective gate resistors when each of the first and second MOS transistor groups is changed from a turn-off state to a turn-on state.
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Abstract
The present invention relates to a switch circuit and a single pole double throw (SPDT) circuit. The switch circuit includes: a MOS transistor transferring or blocking a signal according to a turn on/off operation thereof; a gate resistor connected to a gate of the MOS transistor; and a variable gate resistor circuit increasing a resistance value of the gate resistor when the MOS transistor is changed from a turn-off state to a turn-on state.
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Citations
4 Claims
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1. An SPDT circuit comprising:
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an antenna; a first MOS transistor group transmitting a transmission signal from a transmitting end to the antenna according to a turn-on operation thereof and blocking introduction of a reception signal received in the antenna into the transmitting end according to a turn-off operation thereof; a first gate resistor group including gate resistors each connected to gates of the respective transistors of the first MOS transistor group; a second MOS transistor group applied with gate power complementary to turn-on gate power of the first MOS transistor group to operate complementarily to the first MOS transistor group, transferring the reception signal to a receiving end, and blocking leakage of the transmission signal to the receiving end; a second gate resistor group including gate resistors each connected to gates of the respective transistors of the second MOS transistor group; and a variable gate resistor circuit group increasing resistance values of the respective gate resistors when each of the first and second MOS transistor groups is changed from a turn-off state to a turn-on state. - View Dependent Claims (2, 3, 4)
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Specification