Inverse taper waveguides for low-loss mode converters

• US 9,709,741 B2
• Filed: 04/30/2015
• Issued: 07/18/2017
• Est. Priority Date: 04/30/2014
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Pan, Huapu, Shen, Xiao, Xu, Qianfan, Zheng, Dawei, Yang, Li
• Primary Examiner(s): Wong, Tina
• Application Number:
  US14/700,892
• Publication Number:
  US 20150316720A1
• Time in Patent Office: 810 Days
• Field of Search: None
• CPC Class Codes: G02B 6/1228 Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/14 Mode converters
• CPC Class Codes: G02B 6/305 and having an integrated mode-size expanding section, e.g. tapered waveguide

Abstract

An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO2) layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Claims

1. An apparatus comprising:

a substrate;

a silicon dioxide (SiO₂) material disposed on top of the substrate;

a silicon waveguide comprising a first adiabatic tapering and fully enclosed in the silicon dioxide material; and

a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering with respect to the substrate so that no portion of the silicon waveguide is between the low-index waveguide and the substrate,

wherein the low-index waveguide comprises a second adiabatic tapering,

wherein the first adiabatic tapering is adjacent to the second adiabatic tapering,

wherein a first width of the first adiabatic tapering is widest at a first location along the substrate, and

wherein a second width of the second adiabatic tapering is narrowest at the first location.

2. The apparatus of claim 1, wherein the silicon dioxide material is integrated with the substrate.

3. The apparatus of claim 1, wherein the silicon dioxide material is separated from the low-index waveguide by air.

4. The apparatus of claim 1, wherein the silicon dioxide material is separated from the low-index waveguide by a low-index material.

5. The apparatus of claim 1, wherein the silicon waveguide is oxidized with the silicon dioxide material.

6. The apparatus of claim 1, wherein the low-index waveguide comprises at least one of silicon dioxide, silicon nitride (Si₃N₄), silicon-rich oxide (SiO_x), aluminum oxide (Al₂O₃), and silicon carbide (SiC).

7. The apparatus of claim 1, wherein the substrate is a silicon-on-insulator (SOI).

8. The apparatus of claim 1, wherein at least a first portion of the first adiabatic tapering is separated from at least a second portion of the second adiabatic tapering by a substantially constant gap.

9. The apparatus of claim 8, wherein the gap is between 50 nanometers (nm) and 1 micrometer (μ

m).

10. The apparatus of claim 1, wherein at least a first portion of the first adiabatic tapering and at least a second portion of the second adiabatic tapering abut each other.

11. The apparatus of claim 1, wherein the silicon dioxide material is separated from the low-index waveguide by a cladding.

12. The apparatus of claim 1, wherein the silicon waveguide comprises a first refractive index, wherein the low-index waveguide comprises a second refractive index, and wherein the second refractive index is lower than the first refractive index.

13. The apparatus of claim 12, wherein the first refractive index is greater than 3.

14. The apparatus of claim 13, wherein the second refractive index is between about 1.4 and 3.

15. The apparatus of claim 1, wherein the silicon dioxide material forms part of a hard mask configured to facilitate tip width reduction of the silicon waveguide via thermal oxidation.

16. An apparatus comprising:

a substrate;

a silicon dioxide (SiO₂) material disposed on top of the substrate;

a silicon waveguide comprising a first adiabatic tapering and fully enclosed in the silicon dioxide material; and

a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering with respect to the substrate so that no portion of the silicon waveguide is between the low-index waveguide and the substrate,

wherein the low-index waveguide comprises a second adiabatic tapering,

wherein the first adiabatic tapering is adjacent to the second adiabatic tapering,

wherein a first width of the first adiabatic tapering is narrowest at a second location along the substrate, and

wherein a second width of the second adiabatic tapering is widest at the second location.

17. An apparatus comprising:

a substrate;

a silicon dioxide (SiO₂) material disposed on top of the substrate;

a silicon waveguide comprising a first adiabatic tapering and fully enclosed in the silicon dioxide material; and

a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering with respect to the substrate so that no portion of the silicon waveguide is between the low-index waveguide and the substrate,

wherein the low-index waveguide comprises a second adiabatic tapering,

wherein the first adiabatic tapering is adjacent to the second adiabatic tapering,

wherein a first width of the first adiabatic tapering is greater than 0.4 micrometers (μ

m) at a first location along the substrate and is between about 50 nanometers (nm) and 60 nm at a second location along the substrate, and

wherein a second width of the second adiabatic tapering is about 1 μ

m at the first location and is 15 μ

m or greater at the second location.

18. The apparatus of claim 17, wherein a first thickness of the silicon waveguide is about 0.18 μ

m at the first location and about 0.15 μ

m at the second location, and wherein a second thickness of the silicon waveguide is between about 1 μ

m and about 15 μ

m at the first location and the second location.