Power up body bias circuits and methods

• US 9,710,006 B2
• Filed: 07/25/2014
• Issued: 07/18/2017
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Boling, Edward J.
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US14/341,733
• Publication Number:
  US 20160026207A1
• Time in Patent Office: 1,089 Days
• Field of Search: 327534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An integrated circuit device can include at least a first body bias circuit configured to generate a first body bias voltage different from power supply voltages of the IC device; at least a first bias control circuit configured to set a first body bias node to a first power supply voltage, and subsequently enabling the first body bias node to be set to the first body bias voltage; and a plurality of first transistors having bodies connected to the first body bias node.

Claims

1. An integrated circuit (IC) device, comprising:

at least a first body bias circuit that receives a first power supply voltage, the first body bias circuit configured to generate a first body bias voltage different from the first power supply voltages of the IC device;

at least a clamp control circuit that receives the first power supply voltage and generates a clamp signal when the clamp control circuit detects a saturation of the first power supply voltage;

at least a first bias control circuit that receives the first power supply voltage, the first body bias voltage and the clamp signal, the first bias control circuit configured to set a first body bias node to the first power supply voltage while the first power supply voltage is developing and until the first power supply voltage has completed developing, and to subsequently enable the first body bias node to be set to the first body bias voltage according to the clamp signal after the first power supply voltage reaches stable level and is saturated; and

a plurality of first transistors having bodies connected to the first body bias node.

2. The IC device of claim 1, wherein:

the first bias control circuit includes a depletion mode transistor having a source-drain path coupled between the first power supply voltage and the first body bias node.

3. The IC device of claim 1, further including:

a second body bias circuit that receives the first power supply voltage, the second body bias circuit configured to generate a second body bias voltage different from the first power supply voltages of the IC device and the first body bias voltage;

a second bias control circuit that receives a second power supply voltage, the second body bias voltage and the clamp signal, the second bias control circuit configured to set a second body bias node to the second power supply voltage while the first power supply voltage is developing, and subsequently set the second body bias node to the second body bias voltage according to the clamp signal after the first power supply voltage reaches stable level and is saturated; and

a plurality of second transistors having bodies connected to the second body bias node.

4. The IC device of claim 3, wherein:

the first transistors are n-channel transistors and the second transistors are p-channel transistors.

5. The IC device of claim 1, wherein:

the IC device receives a first high power supply voltage, a second high power supply voltage greater than the first high power supply voltage, and a low power supply voltage;

the first bias control circuit is powered from the second high power supply voltage, and configured to set the first body bias node to the first power supply voltage in response to the second high power supply voltage, and set the first body bias node to the first body bias voltage in response to the first high power supply voltage reaching a predetermined level.

6. The IC device of claim 5, wherein:

the first high power supply voltage is less than 1.5 volts and the second power supply voltage is greater than 1.5 volts.

7. The IC device of claim 1, wherein:

the first bias control circuit includes a clamping transistor having a source-drain path coupled between the first power supply voltage and the first body bias node, and a gate control circuit configured to enable the clamping transistor while the first body bias circuit is developing the first body bias voltage, and disable the clamping transistor when the first body bias voltage is established;

wherein

the clamping transistor is selected from the group of an insulated gate field effect transistor and a junction field effect transistor.

8. The IC device of claim 1, further including:

at least a portion of the first transistors comprise deeply depleted channel (DDC) transistors, each DDC transistor having a screening region formed below a substantially undoped channel, the screening region including

a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ with dopants of a conductivity type opposite to that of a source and drain of the DDC transistor.

18. The IC device of claim 1, wherein:

the first bias control circuit is configured to receive a third power supply voltage and to set the first body bias node to the first power supply voltage or the first body bias voltage according to the third power supply voltage, the third power supply voltage ramps up and is established prior to ramping-up of the first power supply voltage.

9. A method, comprising:

applying a first power supply voltage to an integrated circuit device;

initially clamping at least a first body bias node to the first power supply voltage while the first power supply voltage is developing and until the first power supply voltage has completed developing;

generating at least a first body bias voltage with the first power supply voltage; and

subsequently allowing the first body bias node to be driven by the first body bias voltage after detecting a saturation of the first power supply voltage;

wherein

the first body bias node provides the first body bias voltage to bodies of a plurality of first transistors.

10. The method of claim 9, wherein:

prior to generating the first body bias voltage with the first power supply voltage,

generating a clamp enable signal with a third power supply voltage greater than the first power supply voltage;

wherein

the first body bias node is clamped to the first power supply voltage in response to the clamp enable signal.

11. The method of claim 9, further including:

initially clamping a second body bias node to a second power supply voltage while the first power supply voltage is developing;

generating a second body bias voltage with the first power supply voltage; and

subsequently allowing the second body bias node to be driven with the second body bias voltage after detecting a saturation of the first power supply voltage;

wherein

the second body bias node provides the second body bias voltage to bodies of a plurality of second transistors.

12. The method of claim 11, wherein:

the first body bias voltage is a reverse body bias voltage selected from the group of;

a reverse p-channel body bias voltage (VBP) that is greater than the first power supply voltage, and a reverse n-channel body bias voltage (VBN) that is less than the second power supply voltage.

13. The method of claim 12, wherein:

the reverse VBP ranges from 0.1 volts to 1.0 volts more than the first power supply voltage, and the reverse VBP ranges from 0.1 volts to 1.0 volts less than the second power supply voltage.

14. The method of claim 9, wherein:

at least a portion of the first transistors comprise deeply depleted channel (DDC) transistors, each DDC transistor having a screening region formed below a substantially undoped channel, the screening region including

a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ and with dopants of conductivity type opposite to that of a source and drain of the DDC transistor.

15. An integrated circuit (IC) device, comprising:

a first power supply connection configured to receive a first power supply voltage;

a second power supply connection configured to receive a body bias voltage based on a second power supply voltage greater than the first power supply voltage;

at least a first body bias generator circuit coupled to receive power at a generator power supply node and configured to generate a first body bias voltage;

a switch circuit configured to couple the second power supply connection to the generator power supply node while the first power supply voltage is developing and until the first power supply voltage has completed developing, and to subsequently couple the first power supply connection to the generator power supply node after detecting a saturation of the first power supply voltage; and

a plurality of first transistors having bodies coupled to receive the first body bias voltage.

17. The IC device of claim 15, wherein:

at least a portion of the first transistors comprise deeply depleted channel (DDC) transistors, each DDC transistor having a screening region formed below a substantially undoped channel, the screening region including

a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ with dopants of a conductivity type opposite to that of a source and drain of the DDC transistor.

19. The IC device of claim 15, wherein:

the second power supply voltage rumps up and is established prior to ramping-up of the first power supply voltage.

16. The IC device of 15, further including:

a voltage regulator configured to receive the second power supply voltage and regulate the second power supply voltage to achieve the body bias voltage.