Drift tracking feedback for communication channels

• US 9,710,011 B2
• Filed: 06/26/2015
• Issued: 07/18/2017
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Abhyankar, Abhijit M., Best, Scott C., Chang, Kun-Yung, Lambrecht, Frank
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US14/751,312
• Publication Number:
  US 20150293557A1
• Time in Patent Office: 753 Days
• Field of Search: None
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0033 Correction by delay
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Claims

1. A memory controller comprising:

a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller;

a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount;

a monitoring circuit to monitor the strobe signal and determine the amount of the drift; and

an adjustment circuit to update the sample timing of the data receiver based on the amount of the drift determined by the monitoring circuit.

2. The memory controller of claim 1, further comprising an interface circuit to establish an initial setting for the sample timing of the receiver, the initial setting of the sample timing being established before the update of the sample timing.

3. The memory controller of claim 1, wherein the amount of the drift is due to a change in temperature in an environment of the memory controller.

4. The memory controller of claim 1, further comprising a circuit to calibrate an initial phase for the sample timing of the data receiver.

5. The memory controller of claim 1, further comprising:

a transmitter to output write data;

a circuit to generate a transmit clock signal to time transmission of the write data from the transmitter; and

a circuit to calibrate an initial phase for the transmission of the write data.

6. The memory controller of claim 1 further comprising a receiver circuit to receive a reference clock, wherein a timing of the reference clock controls at least one of transmitting or receiving data.

7. The memory controller of claim 6, further comprising:

a first mixer to generate a transmit clock signal using the reference clock; and

a second mixer to generate a receive clock signal using the reference clock.

8. The memory controller of claim 7, further comprising a calibration circuit to calibrate the transmit clock signal and the receive clock signal while data transfer operations are occurring.

9. The memory controller of claim 8, further comprising calibration logic to initiate the calibration as a result of a change in a system condition of the memory controller being more than a threshold value.

10. The memory controller of claim 8, further comprising calibration logic to initiate the calibration as a result of a software instruction.

11. A method of operation of a memory controller, the method comprising:

receiving a strobe signal, where a phase of the strobe signal has a drift relative to a reference clock by an amount;

sampling data using the strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller;

monitoring the strobe signal to determine the amount of the drift; and

updating, based on the amount of the drift, sample timing for the data being sampled by the strobe signal.

12. The method of claim 11, further comprising:

generating a transmit clock signal using the reference clock

generating a receive clock signal using the reference clock;

transferring data with the memory device in connection with data transfer operations; and

calibrating the transmit clock signal and the receive clock signal while the data transfer operations are occurring.

13. The method of claim 12, wherein the calibration is initiated by a software instruction.

14. The method of claim 12, wherein the calibration is initiated by a change, being more than a threshold value, in a condition of a system in which the memory controller operates.

15. The method of claim 11, further comprising:

generating a set of internal reference clock signals; and

phase mixing the internal reference clock signals in response to a first control signal to generate a receive clock signal, the receive clock signal to be used in the sampling of the data.

16. The method of claim 11, further comprising establishing an initial setting for the sample timing, the initial setting of the sample timing being established before updating sample timing.

17. The method of claim 11, wherein the amount of drift is due to a change in temperature in an environment of the memory controller.

18. The method of claim 11, further comprising calibrating an initial phase for the sample timing for data to be sampled by the strobe signal.

19. The method of claim 11, further comprising:

calibrating an initial phase to transmit write data in connection with a write operation;

generating a transmit clock signal to time transmission of the write data; and

outputting the write data in connection with a write operation.

20. A memory controller comprising:

means for sampling data using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller;

means for receiving the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount;

means for monitoring the strobe signal and means for determining the amount of the drift; and

means for updating sample timing of the data based on the amount of the drift determined by the means for monitoring.