Power shifting in multicore platforms by varying SMT levels

• US 9,710,044 B2
• Filed: 01/23/2015
• Issued: 07/18/2017
• Est. Priority Date: 05/21/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tembey, Priyanka, Da Silva, Dilma M., Bose, Pradip, Buyuktosunoglu, Alper, Franke, Hubertus
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chan, Danny
• Application Number:
  US14/603,722
• Publication Number:
  US 20150134987A1
• Time in Patent Office: 907 Days
• Field of Search: None
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

Claims

1. A method for managing power consumption in a microprocessor platform, the method comprising:

setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications, the multi-core microprocessor platform comprising a plurality of physical cores, each physical core configurable into a plurality of logical cores; and

adjusting a simultaneous multithreading level in at least one physical core by changing a number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level by;

using a power consumption curve of multi-threaded application execution time versus power consumption and a performance curve of level of multi-threading versus amount of speedup in multi-threaded application execution for each physical core to select at least one of one or more physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and one or more physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing the number of logical cores; and

adjusting the simultaneous multithreading level in the selected physical cores to achieve a desired power savings and to maximize performance of the multi-core microprocessor platform in executing multi-threaded applications.

2. The method of claim 1, wherein the step of adjusting the simultaneous multithreading level further comprises adjusting the multithreading level in a plurality of physical cores by changing the number of logical cores on each physical core.

3. The method of claim 2, wherein changing the number of logical cores further comprises decreasing the number of logical cores on at least one physical core and increasing the number of logical cores on at least one physical core.

4. The method of claim 1, wherein the step of adjusting the simultaneous multithreading level further comprises decreasing the number of logical cores for a plurality of physical cores in series until a current power consumption level is less than or equal to the peak power level.

5. The method of claim 4, wherein:

the method further comprises monitoring the current power level consumption continuously; and

repeating the serial decreasing of the number of logical cores through the plurality of physical cores each time the current power consumption level exceeds the peak power level.

6. The method of claim 1, wherein the step of adjusting the simultaneous multithreading level further comprises decreasing the number of logical cores for a given physical core having a lowest number of currently executing instructions per second among the plurality of physical cores.

7. The method of claim 1, wherein the step of adjusting the simultaneous multithreading level further comprises decreasing the number of logical cores for a plurality of physical cores in series based upon a number of currently executing instructions per second on each physical core from a lowest number of instructions per second to a highest number of instructions per second until a current power consumption level is less than or equal to the peak power level.

8. The method of claim 1, wherein the method further comprises monitoring the number of currently executing instructions per second continuously for each one of the plurality of physical cores.

9. The method of claim 1, wherein the step of adjusting the simultaneous multithreading level further comprises adjusting the simultaneous multithreading level in a plurality of physical cores to achieve a desired power savings and to maximize performance of the multi-core microprocessor platform in executing multi-threaded applications.

10. The method of claim 1, wherein the step of adjusting the simultaneous multi-threading level in the selected physical cores comprises shifting the multi-threading level among the selected physical cores by decreasing the number of logical cores on at least one selected physical core and increasing the number of logical cores on at least one selected physical core.

11. The method of claim 1, wherein the step of using the power consumption curve and the performance curve further comprises selecting physical cores that realize power savings without a decrease in performance for a given decrease in multi-threading level of those physical cores.

12. The method of claim 1, wherein the step of using the power consumption curve and the performance curve further comprises selecting physical cores having a largest ratio of power savings to performance decrease for a given decrease in multi-threading level of those physical cores.

13. The method of claim 1, wherein the step of using the power consumption curve and the performance curve further comprises:

identifying physical cores running applications having memory intensive phases during which a given decrease in multi-threading level is possible without a decrease in performance and central processing unit intensive phases in which the given decrease in multi-threading level yields a decrease in performance; and

selecting physical cores during the memory intensive phases.

14. A method for managing power consumption in a microprocessor platform, the method comprising:

setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications, the multi-core microprocessor platform comprising a plurality of physical cores, each physical core configurable into a plurality of logical cores; and

adjusting a simultaneous multithreading level in at least one physical core by changing a number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level by;

arranging the plurality of physical cores into a plurality of bins, each bin comprising a subset of the plurality of physical cores, each physical core in a given bin having a common power consumption curve of multi-threaded application execution time versus power consumption and a common performance curve of level of multi-threading versus amount of speedup in multi-threaded application execution for a given adjustment of multi-threading level;

selecting at least one bin from the plurality of bins, the selected bins comprising at least one of physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing the number of logical cores; and

adjusting simultaneous multi-threading levels for all physical cores in each selected bin.

15. A non-transitory computer-readable storage medium containing a computer-readable code that when read by a computer causes the computer to perform a method for managing power consumption in a microprocessor platform, the method comprising:

setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications, the multi-core microprocessor platform comprising a plurality of physical cores, each physical core configurable into a plurality of logical cores; and

adjusting a simultaneous multithreading level in at least one physical core by changing a number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level by;

using a power consumption curve of multi-threaded application execution time versus power consumption and a performance curve of level of multi-threading versus amount of speedup in multi-threaded application execution for each physical core to select at least one of one or more physical cores from which power consumption can be taken by decreasing multithreading levels while maintaining performance levels thereby decreasing power allocated to physical cores with decreased multithreading levels and one or more physical cores to which power can be shifted to increase multithreading levels to achieve a highest increase in performance level by increasing the number of logical cores; and

adjusting the simultaneous multithreading level in the selected physical cores to achieve a desired power savings and to maximize performance of the multi-core microprocessor platform in executing multi-threaded applications.

16. The non-transitory computer-readable storage medium of claim 15, wherein the step of adjusting the simultaneous multi-threading level in the selected physical cores comprises shifting the multi-threading level among the selected physical cores by decreasing the number of logical cores on at least one selected physical core and increasing the number of logical cores on at least one selected physical core.

17. The non-transitory computer-readable storage medium of claim 15, wherein the step of using the power consumption curve and the performance curve further comprises selecting physical cores that realize power savings without a decrease in performance for a given decrease in multi-threading level of those physical cores.

18. The non-transitory computer-readable storage medium of claim 15, wherein the step of using the power consumption curve and the performance curve further comprises selecting physical cores having a largest ratio of power savings to performance decrease for a given decrease in multi-threading level of those physical cores.

19. The non-transitory computer-readable storage medium of claim 15, wherein the step of using the power consumption curve and the performance curve further comprises:

identifying physical cores running applications having memory intensive phases during which a given decrease in multi-threading level is possible without a decrease in performance and central processing unit intensive phases in which the given decrease in multi-threading level yields a decrease in performance; and

selecting physical cores during the memory intensive phases.

20. The non-transitory computer-readable storage medium of claim 15, wherein the method further comprises monitoring the number of currently executing instructions per second continuously for each one of the plurality of physical cores.