Computer processor with generation renaming
First Claim
Patent Images
1. A processor, comprising:
- a reservation queue;
a renamer coupled to the reservation queue and configured to produce a generation number and to communicate the generation number to the reservation queue;
a register coupled to the reservation queue and configured to store a value;
an execution pipe coupled to the reservation queue; and
a stunt box coupled to the execution pipe, the stunt box comprising;
a first storage, including a plurality of registers, configured to temporarily store an execution pipe result as an intermediate result;
a second storage, communicatively coupled to the first storage, configured to receive and store a plurality of storage results which includes one or more of the intermediate results;
a first arbiter, communicatively coupled to the first storage and the second storage, configured to receive a plurality of intermediate results, and the plurality of storage results and to select an output of the first arbiter to retire from the plurality of intermediate results, and the plurality of storage results;
a second arbiter, communicatively coupled to receive execution pipe results and the output from the first arbiter; and
a third storage, communicatively coupled to receive a plurality of speculative execution pipe results from the second arbiter.
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Abstract
A processor including a register file having a plurality of registers, and configured for out-of-order instruction execution, further includes a renamer unit that produces generation numbers that are associated with register file addresses to provide a renamed version of a register that is temporally offset from an existing version of that register rather than assigning a non-programmer-visible physical register as the renamed register. The processor includes a small reset DHL Gshare branch prediction unit coupled to an instruction cache and configured to provide speculative addresses to the instruction cache.
10 Citations
20 Claims
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1. A processor, comprising:
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a reservation queue; a renamer coupled to the reservation queue and configured to produce a generation number and to communicate the generation number to the reservation queue; a register coupled to the reservation queue and configured to store a value; an execution pipe coupled to the reservation queue; and a stunt box coupled to the execution pipe, the stunt box comprising; a first storage, including a plurality of registers, configured to temporarily store an execution pipe result as an intermediate result; a second storage, communicatively coupled to the first storage, configured to receive and store a plurality of storage results which includes one or more of the intermediate results; a first arbiter, communicatively coupled to the first storage and the second storage, configured to receive a plurality of intermediate results, and the plurality of storage results and to select an output of the first arbiter to retire from the plurality of intermediate results, and the plurality of storage results; a second arbiter, communicatively coupled to receive execution pipe results and the output from the first arbiter; and a third storage, communicatively coupled to receive a plurality of speculative execution pipe results from the second arbiter. - View Dependent Claims (2, 3)
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4. A processor, comprising:
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an instruction cache; an instruction decoder coupled to the instruction cache; a reservation queue coupled to the instruction decoder; a register coupled to the reservation queue and configured to store a value; a renamer coupled to the reservation queue and configured to produce a generation number and to communicate the generation number to the reservation queue; a small reset DHL Gshare branch prediction unit coupled to the instruction cache and configured to generate an address and communicate the address to the instruction cache; a plurality of execution pipes coupled to the reservation queue; and a stunt box coupled to each execution pipe of the plurality of execution pipes, the stunt box comprising; a first storage, including a plurality of registers, configured to temporarily store a plurality of execution pipe results as a plurality of intermediate results; a second storage, communicatively coupled to the first storage, configured to receive and store a plurality of storage results which includes one or more of the plurality of intermediate results; a first arbiter, communicatively coupled to the first storage and the second storage, configured to receive the plurality of intermediate results, and the plurality of storage results and to select an output of the first arbiter to retire from the plurality of intermediate results, and the plurality of storage results; a second arbiter, communicatively coupled to receive execution pipe results and the output from the first arbiter; and a third storage, communicatively coupled to receive a plurality of speculative execution pipe results from the second arbiter.
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5. A processor, comprising:
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an instruction cache; an instruction decoder coupled to the instruction cache; a branch prediction unit coupled to the instruction cache and configured to generate an instruction address and provide the instruction address to the instruction cache; a register file coupled to receive a register address; a renamer unit coupled to the instruction cache and to the instruction decoder; a plurality of reservation queues, each reservation queue of the plurality of reservation queues coupled to the register file, the instruction decoder, and the renamer unit; a plurality of execution pipes, each execution pipe of the plurality of execution pipes coupled to a corresponding one of the plurality of reservation queues, and configured to receive an instruction and data from the corresponding one of the plurality of reservation queues, and to execute the instruction; a stunt box coupled to each execution pipe of the plurality of execution pipes, and configured to receive an output of each execution pipe of the plurality of execution pipes the stunt box comprising; a first storage, including a plurality of registers, configured to temporarily store a plurality of execution pipe results as a plurality of intermediate results; a second storage, communicatively coupled to the first storage, configured to receive and store a plurality of storage results which includes one or more of the plurality of intermediate results; a first arbiter, communicatively coupled to the first storage and the second storage, configured to receive the plurality of intermediate results and the plurality of storage results, and to select an output of the first arbiter to retire from the plurality of intermediate results, and the plurality of storage results; a second arbiter, communicatively coupled to receive execution pipe results and the output from the first arbiter; and a third storage, communicatively coupled to receive a plurality of speculative execution pipe results from the second arbiter; wherein, responsive to an output of the instruction decoder, the register file is configured to provide contents of a register specified as a source in an instruction; and responsive to the output of the instruction decoder, the renamer is configured to concurrently provide a generation number. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification