Multi-array operation support and related devices, systems and software

• US 9,710,377 B1
• Filed: 11/08/2016
• Issued: 07/18/2017
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Kuzmin, Andrey V., Wayda, James G.
• Primary Examiner(s): Bataille, Pierre-Michel
• Application Number:
  US15/346,641
• Time in Patent Office: 252 Days
• Field of Search: 711114, 711103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 16/1847 specifically adapted to static storage, e.g. adapted to flash memory or SSD
• CPC Class Codes: G06F 2015/766 Flash EPROM
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Claims

1. A host device to direct memory access requests to a flash memory controller integrated circuit, the flash memory controller integrated circuit to manage flash memory comprising multiple planes, the host device comprising at least hardware-based processor and instructions stored on non-transitory machine readable media, said instructions when executed to cause the at least one hardware based processor to:

pre-establish a first range of addresses that are to be used for multi-plane writes of data into the flash memory and a second range of addresses that are to be used for single plane writes of data into the flash memory; and

during operation of the host device, cause the host device to direct the memory access requests to the flash memory controller integrated circuit in dependence on whether an address associated with a given one of the memory access requests corresponds to the first range of addresses or to the second range of addresses, wherein the memory access requests are to cause the flash memory controller integrated circuit to access a variable number of the planes in dependence on the address associated with the given one of the memory access requests, such that a first address corresponding to a first memory access request causes the flash memory controller integrated circuit to exchange respective subsets of data associated with the first memory access request with respective ones of the planes, and such that a second address corresponding to a second memory access request causes the flash memory controller integrated circuit to exchange all of the data associated with the second memory access request with a single one of the planes only.

2. The host device of claim 1, wherein the memory controller integrated circuit is to issue memory commands to the flash memory, the memory commands comprising single-plane access commands and multi-plane access commands, and wherein the instructions when executed are to cause the host device to direct the memory access requests such that the flash memory controller integrated circuit issues the memory commands as multi-plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses and as single-plane access commands when the given one of the memory access requests is directed to an address in the second range of addresses.

3. The host device of claim 2, wherein the multi-plane access commands comprise multi-plane read commands, said multi-plane read commands to cause the flash memory to return respective read data from respective ones of the planes according to a common base address specified by a corresponding one of the multi-plane read commands.

4. The host device of claim 1, wherein the memory commands comprise single-plane access commands, and wherein the instructions when executed are to cause the host device to direct the memory commands to the flash memory controller integrated circuit such that the flash memory controller integrated circuit issues multiple single plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses, the multiple single plane access commands to access respective ones of the planes.

5. The host device of claim 4, wherein the host device is to issue at least one of the memory access requests to the flash memory controller integrated circuit as a series of fused commands, wherein each of the fused commands specifies an address within the first range of addresses, and wherein the flash memory controller integrated circuit is to receive each of the fused commands prior to executing any of the fused commands in the series.

6. The host device of claim 1, wherein the instructions when executed are to cause the host device to request a move of data from a source address within the first range of addresses to a destination, and wherein responsive to said move, at least one of the host device or the flash memory controller integrated circuit is to deallocate memory space associated with the source address, such that memory locations in each of the multiple planes corresponding to said memory space are marked for erasure prior to an ensuing write to said memory space.

7. The host device of claim 6, wherein the host device is to issue at least one explicit command to the flash memory controller integrated circuit to cause the flash memory controller integrated circuit to deallocate the memory space.

8. The host device of claim 1, wherein the instructions when executed are to cause the host device to issue a command to the flash memory controller integrated circuit to return to the host device information characterizing the flash memory, the information representing at least one of a number of flash memory channels, a number of the planes, a number of memory flash memory dies, and a number of planes associated with a specific flash memory die.

9. A method of operating a memory system, the memory system comprising a host device and a flash memory controller to manage flash memory comprising multiple planes, the method comprising:

pre-establishing a first range of addresses that are to be used for multi-plane writes of data into the flash memory and a second range of addresses that are to be used for single plane writes of data into the flash memory; and

during operation of the host device, causing the host device to issue memory access requests to the flash memory controller integrated circuit in dependence on whether an address associated with a given one of the memory access requests corresponds to the first range of addresses or to the second range of addresses, wherein the memory access requests are to cause the flash memory controller integrated circuit to access a variable number of the planes in dependence on the address associated with the given one of the memory access requests, such that a first address corresponding to a first memory access request causes the flash memory controller integrated circuit to exchange respective subsets of data associated with the first memory access request with respective ones of the planes, and such that a second address corresponding to a second memory access request causes the flash memory controller integrated circuit to exchange all of the data associated with the second memory access request with a single one of the planes only.

10. The method of claim 9, wherein the memory controller integrated circuit is to issue memory commands to the flash memory, the memory commands comprising single-plane access commands and multi-plane access commands, and wherein the method further comprises causing the flash memory controller integrated circuit to issue the memory commands as multi-plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses and as single-plane access commands when the given one of the memory access requests is directed to an address in the second range of addresses.

11. The method of claim 10, wherein the multi-plane access commands comprise multi-plane read commands, and wherein the method further comprises causing the flash memory controller integrated circuit to read respective data from respective ones of the planes according to a common base address specified by a corresponding one of the multi-plane read commands.

12. The method of claim 9, wherein the memory commands comprise single-plane access commands, and wherein the method further comprises causing the flash memory controller integrated circuit to issue the memory commands as multiple single plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses, the multiple single plane access commands each to be directed by the flash memory controller integrated circuit to access respective ones of the planes.

13. The method of claim 12, wherein the method further comprises causing the host device to issue one of the memory access requests to the flash memory controller integrated circuit as a series of fused commands, wherein each of the fused commands specifies an address within the first range of addresses, and wherein the flash memory controller integrated circuit is to receive each of the fused commands prior to executing any of the fused commands in the series.

14. The method of claim 9, wherein the method further comprises causing the host device to command a move of data from a source address within the first range of addresses to a destination, wherein responsive to said move, at least one of the host device or the flash memory controller integrated circuit is to deallocate memory space associated with the source address, such that memory locations in each of the multiple planes corresponding to said memory space are marked for erasure prior to an ensuing write to said memory space.

15. The method of claim 14, further comprising causing the host device to issue at least one explicit command to the flash memory controller integrated circuit to cause the flash memory controller integrated circuit to deallocate the memory space.

16. The method of claim 9, further comprising causing the host device to issue a command to the flash memory controller integrated circuit to return to the host device information characterizing the flash memory, the information representing at least one of a number of flash memory channels, a number of the planes, a number of memory flash memory dies, and a number of planes associated with a specific flash memory die.

17. An apparatus comprising instructions stored on non-transitory, machine-readable media, the instructions to be executed by at least one hardware processor of a host device to direct memory access requests to a flash memory controller integrated circuit, the flash memory controller integrated circuit to manage flash memory comprising multiple planes, the instructions when executed to cause the at least one hardware based processor to:

pre-establish a first range of addresses that are to be used for multi-plane writes of data into the flash memory and a second range of addresses that are to be used for single plane writes of data into the flash memory; and

during operation of the host device, cause the host device to issue the memory access requests to the flash memory controller integrated circuit in dependence on whether an address associated with a given one of the memory access requests corresponds to the first range of addresses or to the second range of addresses, wherein the memory access requests are to cause the flash memory controller integrated circuit to access a variable number of the planes in dependence on the address associated with the given one of the memory access requests, such that a first address corresponding to a first memory access request causes the flash memory controller integrated circuit to exchange respective subsets of data associated with the first memory access request with respective ones of the planes, and such that a second address corresponding to a second memory access request causes the flash memory controller integrated circuit to exchange all of the data associated with the second memory access request with a single one of the planes only.

18. The apparatus of claim 17, wherein the memory controller integrated circuit is to issue memory commands to the flash memory, the memory commands comprising single-plane access commands and multi-plane access commands, and wherein the instructions when executed are to cause the host device to direct the memory access requests such that the flash memory controller integrated circuit issues the memory commands as multi-plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses and as single-plane access commands when the given one of the memory access requests is directed to an address in the second range of addresses.

19. The apparatus of claim 18, wherein the multi-plane access commands comprise multi-plane read commands, said multi-plane read commands to cause the flash memory to return respective read data from respective ones of the planes according to a common base address specified by a corresponding one of the multi-plane read commands.

20. The apparatus of claim 17, wherein the memory commands comprise single-plane access commands, and wherein the instructions when executed are to cause the host device to direct the memory commands to the flash memory controller integrated circuit such that the flash memory controller integrated circuit issues multiple single plane access commands when the given one of the memory access requests is directed to an address in the first range of addresses, the multiple single plane access commands to access respective ones of the planes.

21. The apparatus of claim 20, wherein the host device is to issue at least one of the memory access requests to the flash memory controller integrated circuit as a series of fused commands, wherein each of the fused commands specifies an address within the first range of addresses, and wherein the flash memory controller integrated circuit is to receive each of the fused commands prior to executing any of the fused commands in the series.

22. The apparatus of claim 17, wherein the instructions when executed are to cause the host device to command a move of data from a source address within the first range of addresses to a destination, and wherein responsive to said move, at least one of the host device or the flash memory controller integrated circuit is to deallocate memory space associated with the source address, such that memory locations in each of the multiple planes corresponding to said memory space are marked for erasure prior to an ensuing write to said memory space.

23. The apparatus of claim 22, wherein the instructions when executed are to cause host device to issue at least one explicit command to the flash memory controller integrated circuit to cause the flash memory controller integrated circuit to deallocate the memory space.

24. The apparatus of claim 17, wherein the instructions when executed are to cause the host device to issue a command to the flash memory controller integrated circuit to return to the host device information characterizing the flash memory, the information representing at least one of a number of flash memory channels, a number of the planes, a number of memory flash memory dies, and a number of planes associated with a specific flash memory die.