Microprocessor architecture having alternative memory access paths

• US 9,710,384 B2
• Filed: 01/04/2008
• Issued: 07/18/2017
• Est. Priority Date: 01/04/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wallach, Steven J., Brewer, Tony
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US11/969,792
• Publication Number:
  US 20090177843A1
• Time in Patent Office: 3,483 Days
• Field of Search: 711131
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]

Abstract

The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.

Claims

1. A system comprising:

non-sequential access memory;

a processor that is operable to process a first portion of instructions included in an executable file;

a communication bus via which the processor sends a second portion of instructions with specific syntax as appearing in the executable file to a heterogeneous functional unit, wherein the first portion of instructions includes first instructions that are recognized by a first instruction set of the processor and the second portion of instructions includes second instructions that are not recognized by the first instruction set of the processor;

the heterogeneous functional unit that is operable to execute the second portion of instructions according to the specific syntax;

cache memory;

a cache-access path in which block data is communicated between said non-sequential access memory and said cache memory for accesses of said block data by said processor for processing said first portion of instructions; and

a direct-access path in which individually-addressed data is communicated to/from said non-sequential access memory for accesses of said individually-addressed data by said heterogeneous functional unit for processing said second portion of instructions.

2. The system of claim 1 wherein in said cache-access path said block data is fetched from said non-sequential access memory for loading to said cache memory.

3. The system of claim 1 wherein in said cache-access path said block data is stored to said non-sequential access memory from said cache memory.

4. The system of claim 1 wherein said processor comprises the first instruction set that defines instructions that are executable by said processor, wherein said heterogeneous functional unit comprises the second instruction set that defines instructions that are executable by said heterogeneous functional unit, and wherein said instructions defined in said first instruction set are not executable by said heterogeneous functional unit, and said instructions defined in said second instruction set are not executable by said processor.

5. The system of claim 1 wherein in said direct-access path said individually-addressed data is fetched from said non-sequential access memory to said heterogeneous functional unit.

6. The system of claim 1 wherein in said direct-access path said individually-addressed data is stored to said non-sequential access memory from said heterogeneous functional unit.

7. The system of claim 1 comprising:

a die on which said processor, said heterogeneous functional unit, and said cache memory are included.

8. The system of claim 1 wherein said processor accesses data via said cache-access path;

and wherein said heterogeneous functional unit is operable to access data via said direct-access path.

9. The system of claim 1 wherein said heterogeneous functional unit comprises a dynamically-reconfigurable instruction set.

10. The system of claim 1 wherein said heterogeneous functional unit comprises a field-programmable gate array (FPGA).

11. The system of claim 1 wherein said non-sequential access memory comprises:

a scatter/gather memory module.

12. The system of claim 1 wherein said non-sequential access memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

13. The system of claim 1 wherein said system enables full bandwidth memory access for non-sequential memory accesses.

14. The system of claim 13 wherein said system further enables full bandwidth memory access for sequential memory accesses.

15. A system comprising:

non-sequential access main memory; and

a die comprising;

cache memory,

a micro-processor core that is operable to process a first portion of instructions included in an executable file and that is operable to access data via a cache-access path in which block data is communicated between said non-sequential access main memory and said cache memory,

a communication bus via which the micro-processor core is operable to send a second portion of instructions with specific syntax as appearing in the executable file to a heterogeneous functional unit, and

the heterogeneous functional unit that is operable to execute the second portion of instructions according to the specific syntax and that is operable to access data via a direct-access path in which individually-addressed data is communicated between said heterogeneous functional unit and said non-sequential access main memory.

16. The system of claim 15 wherein in said cache-access path said block data is fetched from said non-sequential access main memory for loading to said cache memory.

17. The system of claim 15 wherein in said direct-access path said individually-addressed data is fetched from said non-sequential access main memory.

18. The system of claim 15 wherein said non-sequential access main memory comprises:

a scatter/gather memory module.

19. The system of claim 15 wherein said heterogeneous functional unit comprises a dynamically-reconfigurable instruction set.

20. The system of claim 15 wherein said heterogeneous functional unit comprises a field-programmable gate array (FPGA).

21. The system of claim 15 wherein said non-sequential access main memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

22. The system of claim 15 wherein said system enables full bandwidth memory access for non-sequential memory accesses.

51. The system of claim 15 wherein said micro-processor core comprises a first instruction set that defines instructions that are executable by said micro-processor core, wherein said heterogeneous functional unit comprises a second instruction set that defines instructions that are executable by said heterogeneous functional unit, and wherein said instructions defined in said first instruction set are not executable by said heterogeneous functional unit, and said instructions defined in said second instruction set are not executable by said micro-processor core.

23. A method comprising:

decoding, by a processor core of a system, an instruction of an executable file being executed, wherein the executable file includes native instructions that are recognized by a native instruction set of the processor core and extended instructions that are not recognized by the native instruction set of the processor core;

determining, by said processor core, whether the decoded instruction is one of said native instructions or is one of said extended instructions;

when determined that the decoded instruction is one of said native instructions, executing the decoded instruction by said processor core according to said processor core'"'"'s native instruction set, wherein said processor core accesses data for executing said decoded instruction via a cache-access path in which block data is fetched from a non-sequential access main memory of the system for loading to a cache of said system; and

when determined that the decoded instruction is one of said extended instructions, sending the decoded instruction to a heterogeneous functional unit of the system, where the heterogeneous functional unit has an extended instruction set that recognizes said extended instruction, said heterogeneous functional unit being operable to execute the decoded extended instruction according to said extended instruction set, and wherein said heterogeneous functional unit accesses data for executing said decoded extended instruction via a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory.

24. The method of claim 23 wherein said processor core, said cache, and said heterogeneous functional unit are included on a common die.

25. The method of claim 23 wherein said non-sequential access main memory enables retrieval of individually-referenced physical addresses, rather than block-oriented accesses.

26. The method of claim 23 wherein said non-sequential access main memory enables full bandwidth memory access for non-sequential memory accesses.

33. The method of claim 23 wherein said decoding comprises converting the instruction into a machine-readable form.

34. The method of claim 33 wherein said machine-readable form comprises binary form.

35. The method of claim 23 wherein the heterogeneous functional unit receives and executes the decoded extended instruction, in a specific syntax as decoded by said decoding performed by said processor core.

36. The method of claim 35 wherein said decoded extended instruction is a machine-readable equivalent of said extended instruction appearing in the executable file.

52. The method of claim 23 wherein said native instructions are not recognized by said extended instruction set of said heterogeneous functional unit.

27. A system comprising:

a main memory subsystem comprising non-sequential access main memory;

a processing subsystem comprising;

a microprocessor core having a first instruction set for executing a first portion of instructions included in an executable file,

a communication bus via which the microprocessor core is operable to send a second portion of instructions having specific syntax as appearing in the executable file to a heterogeneous functional unit,

the heterogeneous functional unit having a second instruction set for executing the second portion of instructions according to the specific syntax, and

cache memory;

a cache-access path in which block data is fetched from said non-sequential access main memory for loading to said cache memory for processing of said first portion of instructions by said microprocessor core; and

a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory for processing of said second portion of instructions by said heterogeneous functional unit.

28. The system of claim 27 wherein said non-sequential access main memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

29. The system of claim 27 wherein said heterogeneous functional unit is reconfigurable to have as said second instruction set any of a plurality of predefined extended instruction sets for extending the first instruction set such that each extended instruction set provides extended instructions not natively supported by the first instruction set.

30. The system of claim 29 wherein said microprocessor core, said heterogeneous functional unit, and said cache memory are included on a common die.

31. The system of claim 29 wherein said second instruction set extends the first instruction set by providing extended instructions not natively supported by the first instruction set of the microprocessor core.

32. The system of claim 29 wherein said heterogeneous functional unit is reconfigurable to have as said second instruction set any of a plurality of predefined extended instruction sets for extending the first instruction set such that each extended instruction set provides extended instructions not natively supported by the first instruction set.

53. The system of claim 27 wherein each instruction in said first instruction set is not executable by said heterogeneous functional unit, and each instruction in said second instruction set is not executable by said microprocessor core.

37. A system comprising:

non-sequential access memory;

a processor having a first instruction set, said processor operable to execute a first portion of instructions included in an executable file that are defined by the first instruction set, where the executable file includes said first portion of instructions that are defined by the first instruction set and further includes a second portion of instructions that are not defined by the first instruction set;

a communication bus via which the processor sends the second portion of instructions included in the executable file to a heterogeneous co-processor;

the heterogeneous co-processor having an extended instruction set that defines said second portion of instructions, said heterogeneous co-processor operable to execute the second portion of instructions according to its extended instruction set;

cache memory;

a cache-access path in which block data is communicated between said non-sequential access memory and said cache memory for accesses of said block data by said processor for executing said first portion of instructions; and

a direct-access path in which individually-addressed data is communicated to/from said non-sequential access memory for accesses of said individually-addressed data by said heterogeneous co-processor for executing said second portion of instructions.

38. The system of claim 37 wherein in said cache-access path said block data is fetched from said non-sequential access memory for loading to said cache memory.

39. The system of claim 37 wherein in said cache-access path said block data is stored to said non-sequential access memory from said cache memory.

40. The system of claim 37 wherein in said direct-access path said individually-addressed data is fetched from said non-sequential access memory to said heterogeneous co-processor.

41. The system of claim 37 wherein in said direct-access path said individually-addressed data is stored to said non-sequential access memory from said heterogeneous co-processor.

42. The system of claim 37 comprising:

a die on which said processor, said heterogeneous co-processor, and said cache memory are included.

43. The system of claim 37 wherein said processor accesses data via said cache-access path;

and wherein said heterogeneous co-processor is operable to access data via said direct-access path.

44. The system of claim 37 wherein said heterogeneous co-processor comprises dynamically-reconfigurable logic that is reconfigurable to have any of a plurality of different extended instruction sets.

45. The system of claim 44 wherein said dynamically-reconfigurable logic comprises a field-programmable gate array (FPGA).

46. The system of claim 37 wherein said non-sequential access memory comprises:

a scatter/gather memory module.

47. The system of claim 37 wherein said non-sequential access memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

54. The system of claim 37 wherein said first portion of instructions are not defined by the extended instruction set of said heterogeneous co-processor.

48. A method comprising:

decoding, by a processor core of a system, an instruction of an executable file being executed, wherein the processor core has a first instruction set, and wherein the executable file includes first portion of instructions that are defined by the first instruction set of the processor core and further includes a second portion of instructions that are not defined by the first instruction set of the processor core;

determining, by said processor core, whether the decoded instruction is of a first class or a second class, where an instruction defined by the first instruction set of the processor core is of said first class and an instruction that is not defined by the first instruction set of the processor core is of said second class;

when determined that the decoded instruction is of said first class, executing the decoded instruction by said processor core according to said first instruction set, wherein said processor core accesses data for executing said decoded instruction via a cache-access path in which block data is fetched from a non-sequential access main memory of the system for loading to a cache of said system; and

when determined that the decoded instruction is of said second class, sending the decoded instruction to a heterogeneous co-processor of the system, where the heterogeneous co-processor has an extended instruction set that defines said instruction of said second class, said heterogeneous co-processor being operable to execute the instruction of said second class according to said extended instruction set, and wherein said heterogeneous co-processor accesses data for executing said decoded instruction via a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory.

49. The method of claim 48 wherein said processor core, said cache, and said heterogeneous co-processor are included on a common die.

50. The method of claim 48 wherein said non-sequential access main memory enables retrieval of individually-referenced physical addresses, rather than block-oriented accesses.

55. The method of claim 48 wherein a decoded instruction of said first class is not defined by said extended instruction set of said heterogeneous co-processor.