Source core interrupt steering

• US 9,710,408 B2
• Filed: 11/20/2012
• Issued: 07/18/2017
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Veal, Bryan E., Foong, Annie
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): Huynh, Kim T.
• Application Number:
  US13/681,706
• Publication Number:
  US 20130080674A1
• Time in Patent Office: 1,701 Days
• Field of Search: 710260-269, 710200, 710240-244
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Claims

1. At least one non-transitory machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:

receiving a core identifier that corresponds with a source core that is included in a processor;

receiving an input/output request, produced and originating from the source core, that is associated with the core identifier;

storing the core identifier in a memory coupled to the processor;

directing an interrupt, which corresponds to the request, to the source core based on the core identifier;

wherein the processor is coupled to an additional core and the request includes the core identifier.

2. The at least one medium of claim 1, the method comprising directing the interrupt to the source core, but not the additional core, based on the core identifier.

3. The at least one medium of claim 2, the method comprising directing a message-signaled interrupt message to the source core based on the core identifier.

4. The at least one medium of claim 1, the method comprising determining a message-signaled interrupt address based on the core identifier.

5. The at least one medium of claim 1, the method comprising storing the core identifier in the memory before directing the interrupt to the source core.

6. At least one non-transitory machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:

receiving an input/output request, produced and originating from a source core, which includes a message-signaled interrupt (MSI) message that corresponds to one of the source core and an additional core; and

directing an interrupt, which corresponds to the request and the MSI message, to the one of the source core and the additional core based on the MSI message;

wherein the source core and the additional core are included in a processor.

7. The at least one medium of claim 6, the method comprising directing the interrupt to the one of the source core and the additional core independently of a MSI table.

8. The at least one medium of claim 6, the method comprising changing a MSI vector, which is included in the request, after the request has been sent from the source core.

9. The at least one medium of claim 6, the method comprising directing the MSI message, which includes a MSI address, to the source core.

10. The at least one medium of claim 6, the method comprising directing the interrupt to the source core, but not the additional core, based on the MSI message.

11. The at least one medium of claim 6, the method comprising directing the interrupt to the source core based on the MSI message.

12. The at least one medium of claim 6, the method comprising directing the interrupt to the additional core based on the MSI message.

13. The at least one medium of claim 6, wherein the MSI message includes a MSI address and MSI data.

14. The at least one medium of claim 6, wherein the MSI message is included in a field of the request.

15. The at least one medium of claim 6, the method comprising issuing the MSI message onto a bus before directing the interrupt to the one of the source core and the additional core.

16. At least one non-transitory machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:

using a first queue identifier (QID) to associate a first controller request queue with a first processor core;

using a second QID to associate a second controller request queue with a second processor core;

storing a first input/output (I/O) request, which is produced from the first core and is associated with the first QID, in the first queue based on the first QID; and

directing a first interrupt, which corresponds to the first request, to one of the first and second cores based on the first QID.

17. The at least one medium of claim 16, the method comprising directing the first interrupt to the first core, but not the second core, based on the first QID.

18. The at least one medium of claim 17, the method comprising directing a message-signaled interrupt (MSI) message, corresponding to the first request, to the first core based on the first QID.

19. The at least one medium of claim 18, the method comprising determining a MSI address based on the first QID, wherein the first and second queues are separably addressable.

20. The at least one medium of claim 16, the method comprising:

storing a second input/output (I/O) request, which is produced from the second core and is associated with the second QID, in the second queue based on the second QID; and

directing a second interrupt, which corresponds to the second request, to the second core based on the second QID.