Neuromophic system and configuration method thereof

• US 9,710,747 B2
• Filed: 07/10/2014
• Issued: 07/18/2017
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Hongsik, Oh, JaeHee, Jun, Hyun Goo, Kang, Daehwan, Ryoo, Kyung-chang
• Primary Examiner(s): Chen, Alan
• Application Number:
  US14/328,359
• Publication Number:
  US 20150039547A1
• Time in Patent Office: 1,104 Days
• Field of Search: None
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

Claims

1. A method of generating neuron spiking pulses in a neuromorphic system, comprising:

floating one or more selected bit lines connected to target cells, the target cells having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and

stepwisely increasing voltages applied to unselected word lines connected to unselected cells, the unselected cells having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

2. The method of claim 1, further comprising:

setting cells connected to unselected bit lines other than the one or more selected bit lines to the first state before the increasing.

3. The method of claim 1, further comprising:

setting all cells connected to the one or more selected bit lines to the second state;

and setting the target cells to the first state.

4. The method of claim 3, wherein the first state is different from the second state.

5. The method of claim 4, wherein the plurality of memory cells are phase change memory cells.

6. The method of claim 5, wherein the first state is an amorphous state of a phase change material included in each memory cell and the second state is a crystal state of the phase change material.

7. The method of claim 6, wherein the plurality of memory cells transitions from an amorphous state to a crystalline state when the neuron spiking pulse has been generated.

8. The method of claim 4, wherein the first state is a high resistance state and the second state is a low resistance state.

9. The method of claim 1, further comprising:

detecting whether the neuron spiking pulses are output from selected word lines connected to the target cells.

10. The method of claim 9, wherein the increasing and the detecting are iterated until the neuron spiking pulses are generated.

11. The method of claim 9, wherein the detecting comprises determining that one of the voltages applied to the unselected word lines is greater than a sum of the voltage applied to the one or more selected bit lines and voltage drops in unselected memory cells.

12. The method of claim 1, wherein the floating and the increasing are performed contemporaneously.

13. The method of claim 1, wherein at least one of the plurality of memory cells comprises a diode for reducing a current leakage.

14. A neuromorphic system implementing method comprising:

floating one or more selected bit lines connected to target cells, the target cells having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines;

stepwisely increasing voltages applied to unselected word lines connected to unselected cells, the unselected cells having a second state, from among cells connected to the one or more selected bit lines other than the target cells having the first state, to generate neuron spiking pulses; and

providing first and second neuron spiking pulses selected from the neuron spiking pulses to a synaptic circuit including first and second memory cells with a time interval, to implement an STDP (Spike-Timing Dependent Plasticity) algorithm.

15. The method of claim 14, wherein the memory cells are phase change memory cells.

16. The method of claim 15, wherein the first state is an amorphous state of a phase change material included in each memory cell, and the second state is a crystal state of the phase change material.