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Neural network processor

  • US 9,710,748 B2
  • Filed: 12/22/2016
  • Issued: 07/18/2017
  • Est. Priority Date: 05/21/2015
  • Status: Active Grant
First Claim
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1. A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising:

  • a matrix computation unit configured to, for each of the plurality of neural network layers;

    receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, andgenerate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs,wherein the matrix computation unit is configured as a two dimensional systolic array comprising a plurality of cells, wherein the plurality of weight inputs is shifted through a first plurality of cells along a first dimension of the systolic array, and wherein the plurality of activation inputs is shifted through a second plurality of cells along a second dimension of the systolic array; and

    a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers;

    apply an activation function to each of the plurality of accumulated values for the neural network layer generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

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