System and method for detecting design and process defects on a wafer using process monitoring features

• US 9,710,903 B2
• Filed: 06/05/2009
• Issued: 07/18/2017
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Fouquet, Christophe, Saidin, Zain, Edelstein, Sergio, Nanjangud, Savitha, Hess, Carl
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US12/997,855
• Publication Number:
  US 20110276935A1
• Time in Patent Office: 2,965 Days
• Field of Search: 716 51- 52, 716 54, 700121, 382144-145, 382149
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. One system is configured to detect design defects and process defects at locations on a wafer at which images are acquired by an electron beam review subsystem based on defects in a design, additional defects in the design, which are detected by comparing an image of a die in the design printed on the wafer acquired by the electron beam review subsystem to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.

Claims

1. A system configured to detect design and process defects on a wafer, comprising:

an electron beam review subsystem configured to acquire images for a wafer on a design is printed by a manufacturing process; and

a computer subsystem configured to;

inspect the design to detect defects in the design;

compare an image of a die in the design printed on the wafer acquired by the electron beam review subsystem to an image of the die stored in a database to detect additional defects in the design;

determine locations on the wafer at which the images are acquired by the electron beam review subsystem based on the defects in the design, the additional defects in the design, and defects detected on the wafer by a wafer inspection system, wherein the electron beam review subsystem acquires images at the locations determined by the computer subsystem;

detect design defects and process defects at the locations based on the images acquired at the locations by the electron beam review subsystem; and

compare the images acquired at the locations by the electron beam review subsystem with design clips corresponding to the design defects and the process defects to compare the images to design intent, wherein the design clips are extracted from design data for the design of the wafer, and wherein the design data is generated prior to creation of the wafer for which the images are acquired.

2. The system of claim 1, wherein the computer subsystem is further configured to monitor the design defects and the process defects at the locations on multiple wafers based on the images acquired by the electron beam review subsystem at the locations on the multiple wafers.

3. The system of claim 1, wherein the process defects comprise one of systematic process defects, random process defects, and a combination thereof.

4. The system of claim 1, wherein the computer subsystem is further configured to detect the design defects and the process defects by comparing a portion of the image of the die printed on the wafer to one of the design clips.

5. The system of claim 1, wherein the computer subsystem is further configured to, with the design clips, classify the design defects and the process defects based on locations of the design defects and the process defects in the design, impact of the design defects and the process defects on a process window for the manufacturing process, impact of the design defects and the process defects on functionality of a device corresponding to the design, or some combination thereof.

6. The system of claim 1, wherein the computer subsystem is further configured to identify hot spots in the design and determine the locations on the wafer at which the images are acquired by the electron beam review subsystem based on the hot spots in the design, and wherein the electron beam review subsystem acquires the images at the locations determined by the computer subsystem based on the hot spots.

7. The system of claim 1, wherein the additional defects in the design are not detected by the inspection of the design performed by the computer subsystem.

8. The system of claim 1, wherein the computer subsystem is further configured to detect defects on a reticle by process window qualification analysis and determine the locations on the wafer at which the images are acquired by the electron beam review subsystem based on the defects on the reticle, and wherein the electron beam review subsystem acquires the images at the locations determined by the computer subsystem based on the defects on the reticle.

9. The system of claim 1, wherein the computer subsystem is further configured to determine the locations on the wafer at which the images are acquired by the electron beam review subsystem based on defects detected on a reticle by a reticle inspection system, and wherein the electron beam review subsystem acquires the images at the locations determined by the computer subsystem based on the defects detected on the reticle.

10. The system of claim 1, wherein the computer subsystem is further configured to determine the locations on the wafer at which the images are acquired by the electron beam review subsystem based on yield simulation results, and wherein the electron beam review subsystem acquires the images at the locations determined by the computer subsystem based on the yield simulation results.

11. The system of claim 1, wherein the computer subsystem is further configured to acquire information about the defects detected on the wafer by the wafer inspection system from output generated by the wafer inspection system.

12. The system of claim 1, wherein the electron beam review subsystem is further configured to perform critical dimension measurements at the locations.

13. The system of claim 1, wherein the computer subsystem is further configured to characterize the design defects and the process defects detected at the locations.

14. The system of claim 1, wherein the computer subsystem is further configured to compare the images acquired at the locations by the electron beam review subsystem to the design clips to locate the design defects and the process defects at the locations, classify the design defects and the process defects, perform relative measurements of the design defects and the process defects, and perform marginality analysis of the design defects and the process defects.

15. The system of claim 1, wherein the computer subsystem is further configured to overlay defect information from multiple process steps in the manufacturing process to identify a design and process interaction issue.

16. The system of claim 1, wherein the computer subsystem is further configured to perform marginality analysis by performing differential sizing measurements of the design defects and the process defects to determine if the design defects and the process defects are defects or parametric variations, determine if the design defects and the process defects will impact device performance or reliability, and determine marginality of the parametric variations versus pre-set marginality threshold values.

17. The system of claim 16, wherein the computer subsystem is further configured to perform defect classification based on results of the marginality analysis.

18. The system of claim 16, wherein the pre-set marginality threshold values are determined the electron beam review subsystem.

19. The system of claim 1, wherein the computer subsystem is further configured to alter the design to correct the defects in the design.

20. The system of claim 1, wherein the manufacturing process comprises a lithography process, and wherein the computer subsystem is further configured to monitor a process window of the lithography process based on the images and results of process window qualification analysis performed by an inspection tool.

21. The system of claim 1, wherein the computer subsystem is further configured to determine the locations on the wafer at which the images are acquired by the electron beam review subsystem based on results of inspection of a reticle by a reticle inspection system, wherein the manufacturing process comprises a lithography process performed with the reticle, wherein the electron beam review subsystem acquires the images at the locations determined by the computer subsystem based on the results of the inspection of the reticle, and wherein the computer subsystem is further configured to monitor variations in a process window of the lithography process caused by defects detected on the reticle based on the images and the results of the inspection of the reticle.

22. The system of claim 1, wherein the manufacturing process comprises a lithography process, wherein the computer subsystem is further configured to simulate how features in the design print on the wafer at different values of one or more parameters of the lithography process, wherein the different values comprise nominal values corresponding to a center of a process window of the lithography process, and wherein the computer subsystem is further configured to determine values of the one or more parameters at which the features fail, identify one or more of the features that fail at the values of the one or more parameters closest to the nominal values, and select the one or more identified features as the features for monitoring the lithography process.

23. A system configured to review defects on a wafer, comprising:

an electron beam review subsystem configured to acquire images for discrete locations on a wafer on which a design is printed by a manufacturing process; and

a computer subsystem configured to;

determine the discrete locations based on results of process window qualification analysis;

perform defect review at the discrete locations based on the images acquired for the discrete locations by the electron beam review subsystem;

extract images corresponding to the design printed at nominal values of one or more parameters of the manufacturing process from the results of the process window qualification analysis thereby producing extracted images;

create a recipe for monitoring the discrete locations on multiple wafers based on the extracted images;

detect design defects and process defects at the discrete locations based on the images acquired at the discrete locations by the electron beam review subsystem; and

compare the images acquired at the discrete locations by the electron beam review subsystem with design clips corresponding to the design defects and the process defects to compare the images to design intent, wherein the design clips are extracted from design data for the design of the wafer, and wherein the design data is generated prior to creation of the wafer for which the images are acquired.

24. The system of claim 23, wherein the results of the process window qualification analysis comprise defect locations, classification information related to the analysis, and images acquired for the analysis.

25. The system of claim 23, wherein the results of the process window qualification analysis comprise classification information, and wherein the computer subsystem is further configured to, with a file containing the results of the process window qualification analysis, create a recipe for monitoring the discrete locations on multiple wafers.

26. The system of claim 23, wherein the manufacturing process comprises a lithography process, and wherein the computer subsystem is further configured to monitor a process window of the lithography process based on the images acquired for the discrete locations by the electron beam review subsystem and the results of the process window qualification analysis.

27. The system of claim 23, wherein the computer subsystem is further configured to determine the discrete locations based on the results of the process window qualification analysis and results of inspection of a reticle by a reticle inspection system, wherein the manufacturing process comprises a lithography process performed with the reticle, and wherein the computer subsystem is further configured to monitor variations in a process window of the lithography process caused by defects detected on the reticle based on the images and the results of the inspection of the reticle.

28. The system of claim 23, wherein the process window qualification analysis is performed by an inspection system.

29. The system of claim 23, wherein the electron beam review subsystem comprises an optical microscope, wherein the computer subsystem is further configured to identify the discrete locations on the wafer based on images for the discrete locations acquired by the optical microscope and optical patch images for the discrete locations acquired by a wafer inspection system, and wherein the system is further configured to position the discrete locations in a field of view of the electron beam review subsystem based on the identified discrete locations.

30. The system of claim 23, wherein the computer subsystem is further configured to determine if defects exist at the discrete locations based on the images acquired for the discrete locations by the electron beam review subsystem.

31. The system of claim 23, wherein the results of the process window qualification analysis comprise Bossung images, and wherein the computer subsystem is further configured to perform the defect review at the discrete locations by comparing the Bossung images to the images acquired for the discrete locations by the electron beam review subsystem.

32. The system of claim 23, wherein the computer subsystem is further configured to import the results of the process window qualification analysis from a system that performed the process window qualification analysis.

33. The system of claim 23, wherein the computer subsystem is further configured to determine the discrete locations based on the results of the process window qualification analysis, defects in the design detected by inspection of the design, additional defects in the design detected by comparing an image of a die in the design printed on the wafer to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.

34. The system of claim 23, wherein the manufacturing process comprises a lithography process, wherein the computer subsystem is further configured to simulate how features in the design print on the wafer at different values of one or more parameters of the lithography process, wherein the different values comprise nominal values corresponding to a center of a process window of the lithography process, and wherein the computer subsystem is further configured to determine values of the one or more parameters at which the features fail, identify one or more of the features that fail at the values closest to the nominal values, and select the one or more identified features as the features for monitoring the lithography process.

35. A system configured to review defects on a wafer, comprising:

an electron beam review subsystem configured to acquire images for discrete locations on a wafer on which a design is printed by a lithography process performed with a reticle; and

a computer subsystem configured to determine the discrete locations based on results of inspection of the reticle, to perform defect review at the discrete locations based on the images acquired for the discrete locations by the electron beam review subsystem, the results of the inspection of the reticle, and classification of defects detected on the reticle, and to compare the images acquired for the discrete locations by the electron beam review subsystem with design clips corresponding to the defects to compare the images to design intent, wherein the design clips are extracted from design data for the design of the wafer, and wherein the design data is generated prior to creation of the wafer for which the images are acquired.

36. The system of claim 35, wherein the computer subsystem is further configured to monitor variations in a process window of the lithography process caused by the defects detected on the reticle based on the results of the inspection of the reticle and the images acquired for the discrete locations by the electron beam review subsystem.

37. The system of claim 35, wherein the classification of the defects detected on the reticle is performed by a reticle inspection system.

38. The system of claim 35, wherein the discrete locations comprise discrete locations of the detects that affect a process window of the lithography process, discrete locations of the detects that do not affect the process window, discrete locations of the defects that print on the wafer, and discrete locations of the defects that do not print on the wafer such that all marginal defects on the reticle are reviewed and captured.

39. The system of claim 35, wherein the discrete locations comprise discrete locations of defects having a size that renders them undetectable by a bright field optical wafer inspection system, and wherein the computer subsystem is further configured to perform differential sizing analysis of the detects that are undetectable by the bright field optical wafer inspection system.

40. The system of claim 35, wherein the computer subsystem is further configured to perform differential sizing analysis of defects at the discrete locations by comparing feature dimensions in the images acquired for the discrete locations by the electron beam review subsystem to dimensions of neighboring features in the same die as the discrete locations.

41. The system of claim 35, wherein the computer subsystem is further configured to acquire a file from a reticle inspection system, wherein the file comprises the results of the inspection of the reticle, design coordinates, and the design clips, and wherein the computer subsystem is further configured to translate reticle coordinates into wafer coordinates based on the results of the inspection of the reticle, the design coordinates, and the design clips.

42. The system of claim 35, wherein the computer subsystem is further configured to position the discrete locations in a field of view of the electron beam review subsystem based on the design clips corresponding to the defects.

43. The system of claim 35, wherein the computer subsystem is further configured to append the images acquired for the discrete locations by the electron beam review subsystem to a file comprising the results of the inspection of the reticle, and wherein a reticle inspection system is configured to setup a recipe for reticle inspection based on the images appended to the file by the computer subsystem.

44. The system of claim 35, wherein the computer subsystem is further configured to append the images acquired for the discrete locations by the electron beam review subsystem to a file comprising the results of the inspection of the reticle, and wherein a computer-implemented method comprises setting up a recipe for inspection of an additional design based on the images appended to the file by the computer subsystem.

45. The system of claim 35, wherein the computer subsystem is further configured to alter a recipe for inspection of reticles based on results of the detect review at the discrete locations.

46. The system of claim 35, wherein the computer subsystem is coupled to a reticle inspection system such that the computer subsystem sends information to the reticle inspection system and receives information from the reticle inspection system.

47. The system of claim 35, wherein the computer subsystem is further configured to compare the images acquired for the discrete locations to images of a die stored in a database.

48. The system of claim 35, wherein the computer subsystem is further configured to determine the discrete locations based on the results of the inspection of the reticle, defects in the design detected by inspection of the design, additional defects in the design detected by comparing an image of a die in the design printed on the wafer to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.

49. The system of claim 35, wherein the computer subsystem is further configured to determine the discrete locations based on the results of the inspection of the reticle and results of process window qualification analysis performed for the reticle.

50. The system of claim 35, wherein the computer subsystem is further configured to simulate how features in the design print on the wafer at different values of one or more parameters of the lithography process, wherein the different values comprise nominal values corresponding to a center of a process window of the lithography process, and wherein the computer subsystem is further configured to determine values of the one or more parameters at which the features fail, identify one or more of the features that fail at the values closest to the nominal values, and select the one or more identified features as the features for monitoring the lithography process.