Devices including memory arrays, row decoder circuitries and column decoder circuitries

• US 9,711,224 B2
• Filed: 03/13/2015
• Issued: 07/18/2017
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): HOANG, TRI M
• Application Number:
  US14/657,252
• Publication Number:
  US 20160267984A1
• Time in Patent Office: 858 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/10 Decoders

Abstract

Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

Claims

1. A device, comprising:

a semiconductor die having a first level and a second level elevationally above the first level, the die comprising;

an array of memory cells within the second level;

a memory control unit at least partially under the array of memory cells; and

decoder circuitry consisting of a first unit within the first level and a second unit within the second level, the decoder circuitry comprising row decoder circuitry in data communication with the memory control unit and column decoder circuitry in data communication with the memory control unit, one of the row and column decoder circuitries being within the first unit which extends to physically underlie the array of memory cells and the other of the row and column decoder circuitries being within the second unit which is laterally adjacent to the array of memory cells.

2. The device of claim 1 wherein said first unit is entirely under the array of memory cells.

3. The device of claim 1 wherein the row decoder circuitry is within the first unit.

4. The device of claim 1 wherein the column decoder circuitry is within the first unit.

5. The device of claim 1 wherein the memory control unit is entirely under the array of memory cells.

6. The device of claim 5 further comprising an input/output circuit entirely under the array of memory cells.

7. The device of claim 5 further comprising a power management circuit entirely under the array of memory cells.

8. The device of claim 1 being a singulated die.

9. A device, comprising:

a semiconductor die having a first level and a second level elevationally above the first level, die comprising;

an array of memory cells within the second level;

decoder circuitry consisting of D1 decoder circuitry and D2 decoder circuitry, with one of the D1 and D2 decoder circuitries being in a first unit corresponding to row decoder circuitry and the other being in a second unit corresponding to column decoder circuitry; and

one of the first and second units being within the first level and extending at least partially beneath the array of memory cells, and the other of the first and second units within the second level and being entirely laterally outward of the array of memory cells.

10. The device of claim 9 wherein the array is within a tiled architecture.

11. The device of claim 9 wherein the array is within a non-tiled architecture.

12. The device of claim 9 wherein the array of memory cells is an array of NAND memory cells.

13. The device of claim 9 wherein the first unit is at least partially under the array of memory cells.

14. The device of claim 9 wherein the first unit is laterally outward of the array of memory cells.

15. The device of claim 9 further comprising peripheral circuitry;

the peripheral circuitry being circuitry other than the array of memory cells, and other than the D1 and D2 decoder circuitries;

the peripheral circuitry extending to under the array of memory cells.

16. The device of claim 15 wherein the peripheral circuitry includes a memory control unit that extends to under the array of memory cells.

17. A device, comprising:

a semiconductor die having decoder circuitry consisting of a single unit of row decoder circuitry and a single unit of column decoder circuitry, the die comprising;

an array of memory cells;

column decoder circuitry at least partially laterally beneath the array of memory cells;

row decoder circuitry laterally outward of the array of memory cells and not extending under the array of memory cells;

a memory control unit at least partially under the array of memory cells; and

a bonding pad region laterally outward of the array of memory cells.

18. The device of claim 17 wherein the column decoder circuitry is a single unit along an edge of the array of memory cells.

19. The device of claim 17 wherein the column decoder circuitry is within a single unit centrally located relative to the array of memory cells;

wherein outer edges of the unit of column decoder circuitry are directly under the array of memory cells, and wherein a central region of the unit of column decoder circuitry is not directly under the array of memory cells.

20. The device of claim 17 further comprising the array of memory cells being rectangular-shaped and having four primary sides;

the row decoder circuitry being along one of the primary sides and the bonding pad region being along another of the primary sides adjacent said one of the primary sides.

21. The device of claim 17 wherein the array of memory cells is one of two arrays of memory cells, wherein the column decoder circuitry is a single unit between the two arrays of memory cells, and wherein the unit of column decoder circuitry has edge regions extending under the arrays of memory cells and has a central region that is not directly under either of the arrays of memory cells.