Devices including memory arrays, row decoder circuitries and column decoder circuitries
First Claim
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1. A device, comprising:
- a semiconductor die having a first level and a second level elevationally above the first level, the die comprising;
an array of memory cells within the second level;
a memory control unit at least partially under the array of memory cells; and
decoder circuitry consisting of a first unit within the first level and a second unit within the second level, the decoder circuitry comprising row decoder circuitry in data communication with the memory control unit and column decoder circuitry in data communication with the memory control unit, one of the row and column decoder circuitries being within the first unit which extends to physically underlie the array of memory cells and the other of the row and column decoder circuitries being within the second unit which is laterally adjacent to the array of memory cells.
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Abstract
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.
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Citations
21 Claims
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1. A device, comprising:
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a semiconductor die having a first level and a second level elevationally above the first level, the die comprising; an array of memory cells within the second level; a memory control unit at least partially under the array of memory cells; and decoder circuitry consisting of a first unit within the first level and a second unit within the second level, the decoder circuitry comprising row decoder circuitry in data communication with the memory control unit and column decoder circuitry in data communication with the memory control unit, one of the row and column decoder circuitries being within the first unit which extends to physically underlie the array of memory cells and the other of the row and column decoder circuitries being within the second unit which is laterally adjacent to the array of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A device, comprising:
a semiconductor die having a first level and a second level elevationally above the first level, die comprising; an array of memory cells within the second level; decoder circuitry consisting of D1 decoder circuitry and D2 decoder circuitry, with one of the D1 and D2 decoder circuitries being in a first unit corresponding to row decoder circuitry and the other being in a second unit corresponding to column decoder circuitry; and one of the first and second units being within the first level and extending at least partially beneath the array of memory cells, and the other of the first and second units within the second level and being entirely laterally outward of the array of memory cells. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A device, comprising:
a semiconductor die having decoder circuitry consisting of a single unit of row decoder circuitry and a single unit of column decoder circuitry, the die comprising; an array of memory cells; column decoder circuitry at least partially laterally beneath the array of memory cells; row decoder circuitry laterally outward of the array of memory cells and not extending under the array of memory cells; a memory control unit at least partially under the array of memory cells; and a bonding pad region laterally outward of the array of memory cells. - View Dependent Claims (18, 19, 20, 21)
Specification