3D NAND with partial block erase
First Claim
1. An apparatus, comprising:
- a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line, the first select transistor connected to a first bit line;
a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line physically shorted to the first word line, the second select transistor connected to the first bit line; and
a control circuit configured to set the first bit line to a selected bit line voltage at a first point in time during a memory operation, the control circuit configured to set a gate of the first select transistor to a first voltage at the first point in time and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time.
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Accused Products
Abstract
Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.
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Citations
19 Claims
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1. An apparatus, comprising:
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a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line, the first select transistor connected to a first bit line; a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line physically shorted to the first word line, the second select transistor connected to the first bit line; and a control circuit configured to set the first bit line to a selected bit line voltage at a first point in time during a memory operation, the control circuit configured to set a gate of the first select transistor to a first voltage at the first point in time and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus, comprising:
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a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line finger, a drain of the first select transistor directly connected to a first bit line; a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line finger that is physically shorted to the first word line finger, a drain of the second select transistor directly connected to the first bit line; and one or more control circuits configured to set a gate of the first select transistor to a first voltage at a first point in time during a memory operation and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification