3D NAND with partial block erase

• US 9,711,229 B1
• Filed: 08/24/2016
• Issued: 07/18/2017
• Est. Priority Date: 08/24/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Rabkin, Peter, Higashitani, Masaaki
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/246,510
• Time in Patent Office: 328 Days
• Field of Search: 36518517, 36518501, 36518505
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/25 based on bulk electronic defects, e.g. trapping of electrons
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.

Claims

1. An apparatus, comprising:

a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line, the first select transistor connected to a first bit line;

a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line physically shorted to the first word line, the second select transistor connected to the first bit line; and

a control circuit configured to set the first bit line to a selected bit line voltage at a first point in time during a memory operation, the control circuit configured to set a gate of the first select transistor to a first voltage at the first point in time and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time.

2. The apparatus of claim 1, wherein:

the first NAND string comprises a crystalline silicon channel.

3. The apparatus of claim 1, wherein:

the first select transistor is set into a conducting state at the first point in time and the second select transistor is set into a non-conducting state at the first point in time.

4. The apparatus of claim 1, wherein:

the first voltage is at least a transistor threshold voltage of the first select transistor less than the second voltage.

5. The apparatus of claim 1, wherein:

the memory operation comprises an erase operation; and

the control circuit configured to set a first voltage difference between the gate of the first select transistor and the first bit line such that a gate induced drain leakage current occurs within a channel of the first NAND string during the erase operation.

6. The apparatus of claim 1, further comprising:

a third NAND string including a third memory cell transistor and a third select transistor, a gate of the third memory cell transistor connected to the first word line, the third select transistor connected to a third bit line.

7. The apparatus of claim 6, wherein:

the control circuit configured to float the third bit line during the memory operation.

8. The apparatus of claim 6, wherein:

the control circuit configured to set a gate of the third select transistor to the first voltage during the memory operation.

9. The apparatus of claim 1, further comprising:

a third NAND string including a third memory cell transistor and a third select transistor, a gate of the third memory cell transistor connected to the first word line, the third select transistor connected to a third bit line, the control circuit configured to set the third bit line to the selected bit line voltage during the memory operation.

10. The apparatus of claim 1, wherein:

the first NAND string comprises a vertical NAND string; and

the first select transistor comprises a first drain-side select transistor.

11. The apparatus of claim 1, wherein:

the first NAND string includes a first source-side select transistor; and

the second NAND string includes a second source-side select transistor, the control circuit configured to float a gate of the first source-side select transistor and a gate of second source-side select transistor during the memory operation.

12. An apparatus, comprising:

a first NAND string including a first memory cell transistor in series with a first select transistor, a gate of the first memory cell transistor connected to a first word line finger, a drain of the first select transistor directly connected to a first bit line;

a second NAND string including a second memory cell transistor in series with a second select transistor, a gate of the second memory cell transistor connected to a second word line finger that is physically shorted to the first word line finger, a drain of the second select transistor directly connected to the first bit line; and

one or more control circuits configured to set a gate of the first select transistor to a first voltage at a first point in time during a memory operation and set a gate of the second select transistor to a second voltage different from the first voltage at the first point in time.

13. The apparatus of claim 12, wherein:

the first select transistor is set into a conducting state at the first point in time and the second select transistor is set into a non-conducting state at the first point in time.

14. The apparatus of claim 12, wherein:

the first voltage is at least a transistor threshold voltage of the first select transistor less than the second voltage.

15. The apparatus of claim 12, wherein:

the memory operation comprises an erase operation.

16. The apparatus of claim 12, further comprising:

a third NAND string including a third memory cell transistor in series with a third select transistor, a gate of the third memory cell transistor connected to the first word line finger, the third select transistor connected to a third bit line.

17. The apparatus of claim 16, wherein:

the one or more control circuits configured to float the third bit line during the memory operation.

18. The apparatus of claim 16, wherein:

the one or more control circuits configured to set a gate of the third select transistor to the first voltage during the memory operation.

19. The apparatus of claim 12, wherein:

the first NAND string comprises a vertical NAND string.