System solution for first read issue using time dependent read voltages

• US 9,711,231 B1
• Filed: 06/24/2016
• Issued: 07/18/2017
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Yip, Chris, Reusswig, Philip, Shah, Grishma, Dogan, Abuzer Azo, Lai, Joanna, Yang, Nian Niles, Chen, Changyuan, Ray, Biswajit, Dunga, Mohan
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/191,898
• Time in Patent Office: 389 Days
• Field of Search: 36518511, 36518524
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1'"'"'s when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

Claims

1. An apparatus, comprising:

a storage device comprising a counter for a block of memory cells, wherein different values of the counter identify different sets of read voltage shifts for the block; and

a controller, the controller is configured to;

in response to a power on event involving the block, set the counter to a first value which is cross-referenced to a largest set of read voltage shifts from among the different sets of read voltage shifts; and

in response to a sensing operation in the block, set the counter to a second value which is cross-referenced to a smallest set of read voltage shifts from among the different sets of read voltage, and periodically increment the counter.

2. The apparatus of claim 1, wherein:

the memory cells are programmed to different programmed data states comprising a lowest programmed data state and a highest programmed data state; and

the largest set of read voltage shifts comprise a negative read voltage shift for the lowest programmed data state and a positive read voltage shift for the highest programmed data state.

3. The apparatus of claim 1, wherein:

the controller is configured to increment the counter to one or more intermediate values which are between the first value and the second value, each of the one or more intermediate values is cross-referenced to the smallest set of read voltage shifts; and

in response to a read command received while the counter has the one or more intermediate values, the controller is configured to cause a read operation involving the block using the smallest set of read voltage shifts.

4. The apparatus of claim 1, wherein:

the controller is configured to increment the counter to an intermediate value which is between the first value and the second value, the intermediate value is cross-referenced to an intermediate set of read voltage shifts from among the different sets of read voltage shifts.

5. The apparatus of claim 4, wherein:

a magnitude of a largest read voltage shift in the intermediate set of read voltage shifts is smaller than a magnitude of a largest read voltage shift in the largest set of read voltage shifts and larger than a magnitude of a largest read voltage shift in the smallest set of read voltage shifts.

6. The apparatus of claim 4, wherein:

in response to a read command received while the counter has the intermediate value, the controller is configured to cause a read operation involving the block using the intermediate set of read voltage shifts.

7. The apparatus of claim 1, wherein:

in response to a read command received while the counter has the first value, the controller is configured to cause a read operation involving the block using the largest set of read voltage shifts.

8. The apparatus of claim 1, wherein:

in response to a read command received while the counter has the second value, the controller is configured to cause a read operation involving the block using the smallest set of read voltage shifts.

9. The apparatus of claim 1, wherein:

at least one value of the counter is cross-referenced to different sets of read voltage shifts which correspond to different temperature ranges.

10. The apparatus of claim 1, wherein:

a time period in which the counter transitions from the second value to the first value is set according to a temperature coefficient.

11. The apparatus of claim 1, wherein:

the block is among a plurality of blocks of memory cells;

the storage device comprises a counter for each block of the plurality of blocks; and

the controller is configured to implement a global clock which periodically increments the counters of the plurality of blocks.

12. The apparatus of claim 1, wherein:

the block of memory cells comprises a stack of alternating control gate and dielectric layers, including one group of control gate layers below another group of control gate layers;

the memory cells are arranged in vertically extending memory holes in the stack;

the memory holes have a width which increases with a height in the stack; and

the different sets of read voltage shifts comprise one group of sets of read voltage shifts for the one group of control gate layers and another group of sets of read voltage shifts for the another group of control gate layers.

13. A method, comprising:

providing a counter for each block of a plurality of blocks of memory cells;

in response to a read command involving a selected block among the plurality of blocks, determining a value of the counter for the selected block, selecting a set of read voltages from among a plurality of sets of read voltages based on the value of the counter for the selected block, and reading the selected block using the selected set of read voltages; and

periodically incrementing the counters of the plurality of blocks using a global clock.

14. The method of claim 13, further comprising:

in response to a power on event involving the plurality of blocks, setting the counters to a first value; and

in response to a read command involving the selected block which is received while the counter for the selected block has the first value, reading the selected block using a largest set of read voltage shifts among a plurality of available sets of read voltage shifts.

15. The method of claim 14, wherein the counter of the select block is incremented to a second value, the method further comprising:

in response to a read command involving the selected block which is received while the counter has the second value, reading the selected block using a smallest set of read voltage shifts among the plurality of available sets of read voltage shifts.

16. The method of claim 13, wherein:

different counters of the plurality of blocks have different values according to a time of a last sensing operation in the different blocks.

17. An apparatus, comprising:

a capacitor;

means for storing a plurality of available sets of read voltage shifts for a block of memory cells;

means for charging up a voltage of the capacitor in response to a power on event involving the block, the voltage of the capacitor decaying over time;

means for, in response to a read command involving the block, identifying a set of read voltage shifts among the plurality of available sets of read voltage shifts based on the voltage of the capacitor; and

means for reading the block using read voltages which are based on the set of read voltage shifts.

18. The apparatus of claim 17, further comprising:

means for mapping different ranges of the voltage to different sets of read voltage shifts among the plurality of available sets of read voltage shifts.

19. The apparatus of claim 17, wherein:

a relatively high value of the voltage is cross-referenced to a set of relatively high read voltage shifts among the plurality of available sets of read voltage shifts; and

a relatively low value of the voltage is cross-referenced to a set of relatively low read voltage shifts among the plurality of available sets of read voltage shifts.

20. The apparatus of claim 17, further comprising:

means for charging up the voltage of the capacitor in response to reading of the block.