Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer

• US 9,711,407 B2
• Filed: 12/16/2010
• Issued: 07/18/2017
• Est. Priority Date: 04/14/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: de Jong, J. L., Lim, Paul, Or-Bach, Zvi, Cronquist, Brian, Beinglass, Israel, Sekar, Deepak C.
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US12/970,602
• Publication Number:
  US 20110092030A1
• Time in Patent Office: 2,406 Days
• Field of Search: 438142, 438458, 438401, 257E21568
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/83894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/10 : including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66272 : Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
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• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
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• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
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• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
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• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
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• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
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• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
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• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Claims

1. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate and a metal layer, said metal layer comprising a majority of aluminum of copper, and

then transferring a first mono-crystalline layer on top of said metal layer,

wherein said metal layer is in-between said, base wafer and said first mono-crystalline layer, and said transferring said first mono-crystalline layer comprises an ion-cut, and

subsequently to said transferring, processing said first mono-crystalline layer to define first transistors,

wherein said processing comprises at least two etch steps respectively defining an isolation for said first transistors and defining gates of said first transistors,

and wherein the method further comprises connecting said first transistors, thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate.

2. The method according to claim 1,

wherein said first transistors are substantially horizontally orientated transistors.

3. The method according to claim 1,

wherein said first transistors are junction-less transistors.

4. The method according to claim 1,

wherein said first transistors comprise at least one FinFet transistor.

5. The method according to claim 1,

wherein at least one of said first transistors has a side gate.

6. The method according to claim 1,

wherein said first transistors comprise at least one p-type transistor and one n-type transistor.

7. A method of manufacturing a semiconductor wafer, the method comprising:

proving a base wafer comprising a semiconductor substrate comprising first transistors and a metal layer, said metal layer comprising a majority of aluminum or copper, and

then transferring a first mono-crystalline layer on top of said metal layer,

wherein said metal layer is in-between said base wafer and said first mono-crystalline layer, and

said transferring said first mono-crystalline layer comprises and ion-cut, and

subsequently to said transferring, processing said first mono-crystalline layer to define second transistors,

wherein said processing comprising at least two etch steps respectively defining an isolation for said second transistors and defining gates of said second transistors,

and wherein the method further comprises connecting said first transistors thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate.

8. The method according to claim 7,

wherein said second transistors comprise at least one FinFet transistor.

9. The method according to claim 7,

wherein at least one of said second transistors has a side gate.

10. The method according to claim 7,

wherein said second transistors comprise at least one p-type transistor and one n-type transistor.

11. The method according to claim 7,

wherein said second transistors are junction-less transistors.

12. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate and a metal layer, said metal layer comprising a majority of aluminum or copper, and

then transferring a first mono-crystalline layer on top of said metal layer,

wherein said metal layer is in-between said base wafer and said first mono-crystalline layer, and

said transferring said first mono-crystalline layer comprising an ion-cut, and

subsequently to said transferring, processing said first mono-crystalline layer to define first transistors,

wherein said processing comprises at least two etch steps respectively defining an isolation for said first transistors and defining gates of said first transistors, and

wherein said first transistors comprise at least one FinFet transistor,

and wherein the method further comprises connecting said first transistors thus forming a first circuit that replaces a second circuit constructed with second transistors formed in said semiconductor substrate.

13. The method according to claim 12,

wherein said first transistors comprise at least one p-type transistor and one n-type transistor.

14. The method according to claim 12,

wherein an optical anneal is performed after said ion-cut to repair damage from said ion-cut.

15. The method according to claim 12,

wherein said first transistors are high k metal gate (HKMG) transistors.

16. The method according to claim 12,

wherein said first mono-crystalline layer is less than 1 micron thick.

17. The method according to claim 12,

wherein said first transistors are substantially horizontally orientated transistors.

18. The method according to claim 12,

wherein at least one of said first transistors has a side gate.