Semiconductor device and method for fabricating the same

• US 9,711,411 B2
• Filed: 12/08/2015
• Issued: 07/18/2017
• Est. Priority Date: 11/10/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Huang, Wei-Hao, Chen, Chun-Lung, Tzou, Shih-Fang, Liao, Kun-Yuan, Lu, Chia-Lin, Chang, Feng-Yi
• Primary Examiner(s): TAYLOR, EARL N
• Application Number:
  US14/963,216
• Publication Number:
  US 20170133274A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a first gate structure and a second gate structure on the substrate;

forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, between the first gate structure and the second gate structure and on the substrate;

removing part of the CESL between the first gate structure and the second gate structure to form a first CESL adjacent to the first gate structure and a second CESL adjacent to a first sidewall of the second gate structure, wherein the first CESL comprises a L-shape and the second CESL comprises a reverse L-shape;

forming an interlayer dielectric (ILD) layer on and contacting the substrate and the CESL after forming the first CESL comprising the L-shape and the second CESL comprising the reverse L-shape; and

forming a contact plug adjacent to a second sidewall of the second gate structure and not forming another contact plug adjacent to the first sidewall of the second gate structure.

2. The method of claim 1, wherein the substrate comprises a fin-shaped structure thereon, the method further comprises:

forming the first gate structure and the second gate structure and at the same time forming a third gate structure on the substrate;

forming a first spacer and a second spacer adjacent to each of the first gate structure, the second gate structure, and the third gate structure;

forming the CESL, wherein the step of forming the CESL further comprises forming the CESL on the third gate structure and between the second gate structure and the third gate structure;

removing part of the CESL between the first gate structure and the second gate structure and at the same time removing part of the CESL between the second gate structure and the third gate structure; and

forming the interlayer dielectric (ILD) layer on the CESL, wherein the step of forming the ILD layer further comprises forming the ILD layer between the first gate structure, the second gate structure, and the third gate structure.

3. The method of claim 2, wherein the first spacer comprises SiCN and the second spacer comprises SiO₂.

4. The method of claim 2, wherein the step of forming the ILD layer further comprising forming the ILD layer to contact the fin-shaped structure.

5. The method of claim 2, further comprising:

performing a replacement metal gate (RMG) process to transform the first gate structure, the second gate structure, and the third gate structure into a first metal gate, a second metal gate, and a third metal gate;

forming a dielectric layer on the first metal gate, the second metal gate, the third metal gate, and the ILD layer; and

forming the contact plug in the dielectric layer and the ILD layer and between the second metal gate and the third metal gate.

6. The method of claim 1, wherein the CESL comprises SiCN.

7. A semiconductor device, comprising:

a substrate;

a first gate structure and a second gate structure on the substrate;

a first contact etch stop layer (CESL) adjacent to a sidewall of the first gate structure and a second CESL adjacent to a first sidewall of the second gate structure, wherein the first CESL comprises a L-shape, the second CESL comprises a reverse L-shape, and the bottom surfaces of the L-shape and the reverse L-shape are coplanar;

an interlayer dielectric (ILD) layer on the substrate and contacting the CESL and the substrate between the first CESL and the second CESL; and

a contact plug adjacent to a second sidewall of the second gate structure and no contact plug is adjacent to the first sidewall of the second gate structure.

8. The semiconductor device of claim 7, wherein the substrate comprises a fin-shaped structure thereon, the semiconductor device further comprises:

a first spacer and a second spacer adjacent to each of the first gate structure and the second gate structure.

9. The semiconductor device of claim 8, wherein the first spacer and the second spacer are I-shaped.

10. The semiconductor device of claim 8, wherein the first spacer comprises SiCN and the second spacer comprises SiO₂.

11. The semiconductor device of claim 7, wherein the first CESL and the second CESL comprise SiCN.

12. The semiconductor device of claim 7, wherein the interlayer dielectric (ILD) layer is between the first CESL and the second CESL.

13. The semiconductor device of claim 8, wherein the ILD layer contacts the first CESL, the second CESL, and the fin-shaped structure.

14. The semiconductor device of claim 8, wherein the top surfaces of the first spacer, the second spacer, the first CESL, the second CESL, and the ILD layer are coplanar.

15. The semiconductor device of claim 8, wherein the bottom surfaces of the first spacer, the second spacer, the first CESL, the second CESL, and the ILD layer are coplanar.