Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
First Claim
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1. A method for making an integrated circuit (IC), comprising at least the following:
- (a) performing initial processing steps on a semiconductor wafer, said initial processing steps including;
patterning a mix of at least a thousand logic cells and fill cells;
said patterning including instantiating at least a first Design of Experiments (DOE), said first DOE comprising at least first and second GATE-snake-open-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each of said GATE-snake-open-configured, NCEM-enabled fill cells;
(i) contains at least one GATE snake feature;
(ii) is geometrically compatible for abutment with said logic cells; and
,(iii) is configured to present an open circuit or excessive resistance in its GATE snake feature(s) as an abnormal condition on a NCEM pad contained within the fill cell, said abnormal condition detectable by voltage contrast (VC) inspection of the pad; and
,wherein the first and second GATE-snake-open-configured, NCEM-enabled fill cells of the first DOE differ in terms of their respective probabilities of detecting an open circuit or excessive resistance in their respective GATE snake feature(s);
(b) determining a presence or absence of an open circuit or excessive resistance in a GATE snake feature by;
performing a voltage contrast examination of GATE-snake-open-configured, NCEM-enabled fill cells in the first DOE; and
,determining whether NCEMs of pads contained in the GATE-snake-open-configured, NCEM-enabled fill cells of said first DOE represent instance(s) of GATE snake open or excessive resistance failure(s); and
,(c) based, at least in part, on results from step (b), selectively performing additional processing, metrology or inspection step(s) on said wafer, and/or on other wafer(s) currently being manufactured using a process flow(s) relevant to the observed failure(s).
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Abstract
Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
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Citations
20 Claims
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1. A method for making an integrated circuit (IC), comprising at least the following:
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(a) performing initial processing steps on a semiconductor wafer, said initial processing steps including; patterning a mix of at least a thousand logic cells and fill cells; said patterning including instantiating at least a first Design of Experiments (DOE), said first DOE comprising at least first and second GATE-snake-open-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each of said GATE-snake-open-configured, NCEM-enabled fill cells; (i) contains at least one GATE snake feature; (ii) is geometrically compatible for abutment with said logic cells; and
,(iii) is configured to present an open circuit or excessive resistance in its GATE snake feature(s) as an abnormal condition on a NCEM pad contained within the fill cell, said abnormal condition detectable by voltage contrast (VC) inspection of the pad; and
,wherein the first and second GATE-snake-open-configured, NCEM-enabled fill cells of the first DOE differ in terms of their respective probabilities of detecting an open circuit or excessive resistance in their respective GATE snake feature(s); (b) determining a presence or absence of an open circuit or excessive resistance in a GATE snake feature by; performing a voltage contrast examination of GATE-snake-open-configured, NCEM-enabled fill cells in the first DOE; and
,determining whether NCEMs of pads contained in the GATE-snake-open-configured, NCEM-enabled fill cells of said first DOE represent instance(s) of GATE snake open or excessive resistance failure(s); and
,(c) based, at least in part, on results from step (b), selectively performing additional processing, metrology or inspection step(s) on said wafer, and/or on other wafer(s) currently being manufactured using a process flow(s) relevant to the observed failure(s). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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InventorsDe, Indranil, Hess, Christopher, Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu, Haigh, Jonathan, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav
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Primary Examiner(s)Nikmanesh, Seahvosh
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Application NumberUS15/258,432Time in Patent Office314 DaysField of SearchUS Class CurrentCPC Class CodesG01R 31/2884 using dedicated test connec...G06F 11/079 Root cause analysis, i.e. e...G06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 2027/11866 Gate electrode terminals or...H01L 2027/11875 Wiring region, routingH01L 2027/11885 Two levels of metalH01L 2027/11887 Three levels of metalH01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/34 Circuits for electrically c...H01L 23/5226 Via connections in a multil...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/11803 using field effect technologyH01L 27/11807 CMOS gate arraysH01L 29/0649 Dielectric regions, e.g. Si...H01L 29/0684 characterised by the shape,...View All
