Semiconductor device with coils in different wiring layers

• US 9,711,451 B2
• Filed: 01/29/2014
• Issued: 07/18/2017
• Est. Priority Date: 01/29/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Igarashi, Takayuki, Funaya, Takuo
• Primary Examiner(s): Ingham, John C
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US14/418,116
• Publication Number:
  US 20160027732A1
• Time in Patent Office: 1,266 Days
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]

Abstract

Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

Claims

1. A semiconductor device comprising:

a substrate having a main surface;

a first insulating film formed on the main surface of the substrate;

a first coil and a first wiring formed on the first insulating film;

a second insulating film formed on the first coil and the first wiring;

a second wiring formed on the second insulating film;

a third insulating film formed on the second wiring; and

a second coil and a third wiring formed on the third insulating film,

wherein the first coil and a third wiring formed on the third insulating film,

wherein a shortest distance between the second coil and the third wiring is longer than a shortest distance between the first coil and the second coil in a cross section view, and

wherein a wiring is not arranged along the shortest distance between the second coil and the third wiring in the cross section view.

2. The semiconductor device according to claim 1,

wherein a shortest distance between the second coil and the second wiring is longer than the shortest distance between the first coil and the second coil in the cross section view, and

wherein a wiring is not arranged along the shortest distance between the second coil and the second wiring.

3. The semiconductor device according to claim 2,

wherein a wiring is not arranged between the first and the second coils in the cross section view.

4. The semiconductor device according to claim 1,

wherein each of the second wiring, the second coil and the third wiring has a film thickness of 3 μ

m or more in a thickness direction of the substrate.

5. The semiconductor device according to claim 4,

wherein each of the second insulating film and the third insulating film is formed of an inorganic insulating film.

6. The semiconductor device according to claim 5,

wherein a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil is 5 μ

m or more in the thickness direction.

7. The semiconductor device according to claim 1,

wherein the shortest distance between the second coil and the third wiring is longer than a shortest distance between the second coil and the second wiring in the cross section view.

8. The semiconductor device according to claim 1,

wherein the second coil includes a first pad, a second pad, and a coil portion surrounding the first pad,

wherein one end portion of the coil portion is connected to the first pad,

wherein the other end portion of the coil portion is connected to the second pad, and

wherein each of the first and the second pads has a planar shape formed into a polygonal shape having more sides than those of a square shape.

9. The semiconductor device according to claim 1,

wherein the second wiring and the third wiring are connected to each other in an opening formed in the third insulating film, and the opening has a planar shape formed into a polygonal shape having more sides than those of a square shape.

10. A semiconductor device comprising:

a first semiconductor chip mounted on a first die pad;

a second semiconductor chip mounted side by side with the first semiconductor chip on a second die pad;

a plurality of leads arranged outside the first and the second die pad;

the plurality of leads including a plurality of first leads which are arranged closer to the first semiconductor chip than the second semiconductor chip, and a plurality of second leads which are arranged closer to the second semiconductor chip than the first semiconductor chip and which are arranged opposite to the first leads;

a plurality of bonding wires including a plurality of first wires which connect the first lead and the first semiconductor chip, a plurality of second wires which connect the second leads and the second semiconductor chip, and a plurality of third wires which connect the first and the second semiconductor chips; and

a resin sealing the first and the second semiconductor chips, the first and the second die pads, the bonding wires, and a portion of each of the leads,

wherein the first die pad is not electrically connected with the second die pad,

wherein the first semiconductor chip comprises;

a semiconductor substrate having a main surface;

a first insulating film formed on the main surface of the semiconductor substrate; and

a plurality of wiring layers formed on the first insulating film,

the plurality of wiring layers including a first wiring layer, a second wiring layer, and a third wiring layer,

the first wiring layer formed on the first insulating film and including a first coil and a first wiring which are covered with a second insulating film,

the second wiring layer formed on the second insulating film and including a second wiring covered with a third insulating film,

the third wiring layer formed on the third insulating film and including a third wiring and a second coil which is overlapped with the first coil in a plan view,

wherein a shortest distance between the second coil and the third wiring is longer than a shortest distance between the first coil and the second coil in a cross section view, and

wherein a wiring is not arranged along the shortest distance between the second coil and the third wiring in the cross section view.

11. The semiconductor device according to claim 10,

wherein a shortest distance between the second coil and the second wiring is longer than the shortest distance between the first coil and the second coil in the cross section view, and

wherein a wiring is not arranged along the shortest distance between the second coil and the second wiring.

12. The semiconductor device according to claim 11,

wherein a wiring is not arranged between the first and the second coils in the cross section view.

13. The semiconductor device according to claim 10,

wherein the second coil and the third wiring are covered with a fourth insulating film.

14. The semiconductor device according to claim 13,

wherein each of the second and the third insulating films is formed of an inorganic insulating film.

15. The semiconductor device according to claim 14,

wherein each of the second wiring, the second coil and the third wiring has a film thickness of 3 μ

m or more in a thickness direction of the semiconductor substrate.

16. The semiconductor device according to claim 15,

wherein a sum of film thicknesses of the second insulating film and the third insulating film that are positioned between the first coil and the second coil is 5 μ

m or more in the thickness direction.

17. The semiconductor device according to claim 13,

wherein the shortest distance between the second coil and the third wiring is longer than a shortest distance between the second coil and the second wiring in a cross section view.

18. The semiconductor device according to claim 10,

wherein the second coil includes a first pad, a second pad, and a coil portion surrounding the first pad,

wherein one end portion of the coil portion is connected to the first pad,

wherein the other end portion of the coil portion is connected to the second pad, and

wherein each of the first and the second pads has a planar shape formed into a polygonal shape having more sides than those of a square shape.

19. The semiconductor device according to claim 10,

wherein the second wiring and the third wiring are connected to each other in an opening formed in the third insulating film in the cross section view, and the opening has a planar shape formed into a polygonal shape having more side than those of a square shape.