Separate N and P fin etching for reduced CMOS device leakage

• US 9,711,507 B1
• Filed: 09/30/2016
• Issued: 07/18/2017
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chu, Isabel C., Clevenger, Leigh Anne H., Ebrish, Mona A., Priyadarshini, Deepika, Clevenger, Lawrence A., Karve, Gauri, Seshadri, Indira P., Lie, Fee Li, Saulnier, Nicole A.
• Primary Examiner(s): Bachner, Robert
• Application Number:
  US15/281,970
• Time in Patent Office: 291 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.

Claims

1. A method for forming a semiconductor device, the method comprising:

blocking a first region of a wafer;

forming a plurality of fins in a second region of the wafer;

depositing a conformal mask layer over the plurality of fins in the second region;

unblocking the first region of the wafer;

blocking the second region of the wafer;

forming a plurality of fins in the first region of the wafer;

unblocking the second region of the wafer; and

removing the conformal mask layer.

2. The method of claim 1, wherein the first region of the wafer comprises a substrate, a channel region, and a dielectric layer.

3. The method of claim 1, wherein the second region of the wafer comprises a substrate and a dielectric layer.

4. The method of claim 1, wherein the conformal mask layer comprises a high-k material.

5. The method of claim 4, wherein the high-k material comprises hafnium oxide.

6. The method of claim 1, wherein a critical dimension of the plurality of fins in the first region of the wafer is substantially the same as a critical dimension of the plurality of fins in the second region of the wafer.

7. The method of claim 1, further comprising depositing an oxide fill between the plurality of fins in the second region after depositing the conformal mask layer.

8. The method of claim 1, wherein blocking the first region of the wafer further comprises depositing a conformal oxide spacer and an organic planarization layer over the first region.

9. The method of claim 1, wherein forming the plurality of fins in the second region of the wafer further comprises etching a substrate and a dielectric layer to form the plurality of fins in the second region of the wafer.

10. The method of claim 9, wherein the dielectric layer comprises a nitride material.

11. The method of claim 1, wherein forming the plurality of fins in the first region of the wafer further comprises etching a substrate, a dielectric layer, and a channel material to form the plurality of fins in the first region of the wafer.

12. The method of claim 1, further comprising epitaxially growing a channel material on a substrate to form a channel region.

13. The method of claim 12, wherein the channel material comprises an alloy having the formula

Si(_1-x)M_x,

wherein M is at least one element selected from tin, boron, aluminum, gallium, indium, nitrogen, phosphorous, arsenic, antimony, and bismuth, and

wherein 0<

x<

1.

14. The method of claim 1, wherein depositing the conformal mask layer over the plurality of fins in the second region further comprises filling a region between the plurality of fins in the second region with the conformal mask layer and pinching off at least a portion of the conformal mask layer from above the plurality of fins.