Semiconductor device
First Claim
1. A semiconductor device including a trench-gate type field effect transistor configuring a power transistor in a transistor formation region on a main surface of a semiconductor substrate, comprising:
- a first trench formed in the transistor formation region of the semiconductor substrate;
a first electrode formed in a lower portion inside the first trench;
a gate electrode for the trench-gate type field effect transistor formed in an upper portion inside the first trench;
a first insulating film formed between the first electrode and a side wall and a bottom surface of the first trench;
a second insulating film formed between the gate electrode and a side wall of the first trench;
a third insulating film formed between the first electrode and the gate electrode;
a semiconductor region for a source of a first conductive type formed in a region which is adjacent to the first trench in the semiconductor substrate, a semiconductor region for channel formation of a second conductive type opposite to the first conductive type positioned below the semiconductor region for a source, and a semiconductor region for a drain of the first conductive type positioned below the semiconductor region for a channel formation;
an interlayer insulating film formed on the main surface of the semiconductor substrate;
a wiring for a source formed on the interlayer insulating film and electrically connected to the semiconductor region for a source;
a wiring for a gate formed on the interlayer insulating film and electrically connected to the gate electrode; and
a first wiring formed on the interlayer insulating film and electrically connected to the first electrode,wherein the first wiring is not connected to the wiring for a source through a conductor, and is not connected to the wiring for a gate through a conductor,the semiconductor device further comprisesa second trench formed in the semiconductor substrate in periphery of the transistor formation region and connected to the first trench,a contact hole for a gate formed in the interlayer insulating film in a region where the second trench and the wiring for a gate overlap with each other when seen in a plan view, anda first contact hole formed in the interlayer insulating film in a region where the second trench and the first wiring overlap with each other when seen in a plan view,the second trench includes a first region in which the first electrode and the gate electrode are embedded and a second region in which the first electrode is embedded but the gate electrode is not embedded,the first electrode is formed in a lower portion inside the first region of the second trench through the first insulating film, the gate electrode is formed in an upper portion inside the first region of the second trench through the second insulating film, and the third insulating film is formed between the first electrode and the gate electrode inside the first region of the second trench,the first electrode is formed inside the second region of the second trench through the first insulating film,the contact hole for a gate is formed above the first region of the second trench, and the wiring for a gate is electrically connected to the gate electrode exposed from the contact hole for a gate, andthe first contact hole is formed above the second region of the second trench, and the first wiring is electrically connected to the first electrode exposed from the first contact hole.
2 Assignments
0 Petitions
Accused Products
Abstract
A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
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Citations
19 Claims
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1. A semiconductor device including a trench-gate type field effect transistor configuring a power transistor in a transistor formation region on a main surface of a semiconductor substrate, comprising:
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a first trench formed in the transistor formation region of the semiconductor substrate; a first electrode formed in a lower portion inside the first trench; a gate electrode for the trench-gate type field effect transistor formed in an upper portion inside the first trench; a first insulating film formed between the first electrode and a side wall and a bottom surface of the first trench; a second insulating film formed between the gate electrode and a side wall of the first trench; a third insulating film formed between the first electrode and the gate electrode; a semiconductor region for a source of a first conductive type formed in a region which is adjacent to the first trench in the semiconductor substrate, a semiconductor region for channel formation of a second conductive type opposite to the first conductive type positioned below the semiconductor region for a source, and a semiconductor region for a drain of the first conductive type positioned below the semiconductor region for a channel formation; an interlayer insulating film formed on the main surface of the semiconductor substrate; a wiring for a source formed on the interlayer insulating film and electrically connected to the semiconductor region for a source; a wiring for a gate formed on the interlayer insulating film and electrically connected to the gate electrode; and a first wiring formed on the interlayer insulating film and electrically connected to the first electrode, wherein the first wiring is not connected to the wiring for a source through a conductor, and is not connected to the wiring for a gate through a conductor, the semiconductor device further comprises a second trench formed in the semiconductor substrate in periphery of the transistor formation region and connected to the first trench, a contact hole for a gate formed in the interlayer insulating film in a region where the second trench and the wiring for a gate overlap with each other when seen in a plan view, and a first contact hole formed in the interlayer insulating film in a region where the second trench and the first wiring overlap with each other when seen in a plan view, the second trench includes a first region in which the first electrode and the gate electrode are embedded and a second region in which the first electrode is embedded but the gate electrode is not embedded, the first electrode is formed in a lower portion inside the first region of the second trench through the first insulating film, the gate electrode is formed in an upper portion inside the first region of the second trench through the second insulating film, and the third insulating film is formed between the first electrode and the gate electrode inside the first region of the second trench, the first electrode is formed inside the second region of the second trench through the first insulating film, the contact hole for a gate is formed above the first region of the second trench, and the wiring for a gate is electrically connected to the gate electrode exposed from the contact hole for a gate, and the first contact hole is formed above the second region of the second trench, and the first wiring is electrically connected to the first electrode exposed from the first contact hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification