Semiconductor device with cell trench structures and a contact structure

• US 9,711,641 B2
• Filed: 06/21/2016
• Issued: 07/18/2017
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Cotorogea, Maria
• Primary Examiner(s): Vu, David
• Application Number:
  US15/188,217
• Publication Number:
  US 20160300945A1
• Time in Patent Office: 392 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

Claims

1. A semiconductor device, comprising:

a first and a second cell trench structure extending from a first surface into a semiconductor body, wherein a first semiconductor mesa separates the first and second cell trench structures, the first cell trench structure comprises a first buried electrode and a first insulator layer, a first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa, and the first semiconductor mesa comprises a source zone of a first conductivity type directly adjoining the first surface;

a capping layer on the first surface; and

a contact structure comprising a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode, wherein a lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

2. The semiconductor device of claim 1, wherein the source zone and a body zone of a second conductivity type form a pn junction at a first distance to the first surface and a vertical extension of the second section of the contact structure exceeds the first distance.

3. The semiconductor device of claim 2, wherein in the body zone a maximum impurity concentration of impurities of the second conductivity type has a greater distance to the first surface than the pn junction between the source and body zones.

4. The semiconductor device of claim 1, wherein a plurality of spatially separated source zones is arranged along the first semiconductor mesa.

5. The semiconductor device of claim 1, further comprising:

a heavily doped termination zone of the second conductivity type in an edge area that is devoid of functional IGFET cells and that surrounds a cell area including functional IGFET cells, wherein

for corresponding distances to the first surface, in the termination zone a concentration of impurities of the second conductivity type is higher than a concentration of impurities of the first conductivity type in the source zone.

6. The semiconductor device of claim 1, further comprising:

an auxiliary contact arranged in an edge area that is devoid of functional IGFET cells and that surrounds a cell area including functional IGFET cells,

wherein the auxiliary contact comprises a first section in an opening of the capping layer and a second section extending into the semiconductor body between a semiconductor mesa and a cell trench structure.

7. The semiconductor device of claim 6, wherein the auxiliary contact directly adjoins second semiconductor mesas between first cell trench structures.

8. The semiconductor device of claim 6, further comprising:

an orthogonal second cell trench structure intersecting and connecting a plurality of second cell trench structures; and

third cell trench structures in the lateral projection of the first and second cell trench structures and third semiconductor mesas in the lateral projection of the first and second semiconductor mesas, wherein the third cell trench structures and the third semiconductor mesas are arranged on a side of the orthogonal second cell trench structure oriented to the edge area and the auxiliary contact directly adjoins the third semiconductor mesas.

9. The semiconductor device of claim 6, wherein the second buried electrodes are recessed in an idle portion of the edge area and the auxiliary contact directly adjoins the first and second semiconductor mesas in the idle portion.