Transistors incorporating metal quantum dots into doped source and drain regions

• US 9,711,649 B2
• Filed: 12/29/2015
• Issued: 07/18/2017
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Primary Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US14/983,276
• Publication Number:
  US 20160149051A1
• Time in Patent Office: 567 Days
• Field of Search: 257 20, 438270
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 : with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Claims

1. A method, comprising:

forming an isolation trench in a silicon substrate;

implanting dopants into the silicon substrate in an area enclosed by the isolation trench to form a doped silicon region;

removing doped silicon material from a central portion of the doped silicon region to form a recessed area separating the doped silicon region into two separate areas that are doped source and drain regions;

forming an epitaxial channel in the recessed area;

forming in the recessed area a recessed gate that includes a gate dielectric having a high dielectric constant;

forming a metal quantum dot in the doped source region as an exposed contact for the doped source region, the metal quantum dot having a diameter between 1 and 100 nm and a crystalline structure that is different from a crystalline structure of the doped source region; and

forming a metal quantum dot in the doped drain region as an exposed contact for the doped drain region, the metal quantum dot of size 1-100 nm and a crystalline structure that is different from a crystalline structure of the doped drain region.

2. The method of claim 1, wherein the forming a metal quantum dot further includes

forming a single quantum dot opening in each one of the doped source and drain regions in accordance with a quantum dot array design;

depositing a metal layer in the single quantum dot openings; and

reacting the metal layer with the underlying doped silicon region to form a metal silicide, the metal silicide being different for p-type and n-type dopants depending on which dopant is present in the underlying doped silicon region.

3. The method of claim 2 wherein forming the quantum dot openings includes etching the quantum dot openings so as to have diameters at least as large as the respective metal quantum dot and in a range of 1-100 nm.

4. The method of claim 2, further comprising performing a metal planarization process to planarize the recessed gate and the metal quantum dots.

5. The method of claim 2 wherein the quantum dot array design is an offset array that packs quantum dot devices into a higher density matrix than a square array.

6. The method of claim 5 wherein the quantum dot array design includes quantum dots having one or more of circular, square, diamond, hexagonal, elliptical, or oblong geometries.

7. The method of claim 1 wherein implanting includes implanting the substrate with ions to a selected target depth and to a selected dopant concentration within a range of about 1.0 E19-1.0 E21 atoms/cm³.

8. The method of claim 1 wherein the doped silicon region has a selected dopant profile and the recessed gate area has an etch profile that extends deeper than the dopant profile.

9. The method of claim 1 wherein the epitaxial channel is non-planar and the non-planar epitaxial channel wraps around the recessed gate.

10. A method comprising:

forming a transistor on a substrate, the transistor having a doped source region, a doped drain region, and a conducting channel extending between the doped source and drain regions, the doped source and drain regions providing charge carrier reservoirs for injection of charge into the conducting channel; and

forming respective metal quantum dots in central areas of the doped source and drain regions as contacts for the doped source and drain regions, respectively, each of the metal quantum dots of size 1-100 nm and having a crystalline structure selected to be different from a crystalline structure of silicon.

11. The method of claim 10 wherein forming the transistor includes forming an isolation region and, after the isolation region is formed, doping an entire area of the substrate located within the isolation region, including the doped source and drain regions.

12. The method of claim 11 wherein forming the transistor further includes forming a recessed metal gate, by

selectively removing a portion of the doped substrate within the isolation region and between the doped source and drain regions to form a central recessed area;

and

depositing a metal gate in the central recessed area.

13. The method of claim 12 wherein forming metal quantum dots includes depositing metal in the central areas of the source and drain regions at a same time as depositing the metal gate in the central recessed area.

14. The method of claim 13 wherein depositing metal in the central areas of the source and drain regions and in the central recessed area includes depositing one or more of tungsten, copper, silver, gold, aluminum, or combinations thereof.

15. A method, comprising:

forming an isolation region in a silicon substrate;

growing a doped epitaxial layer to completely cover the isolation region;

removing material from a central portion of the doped epitaxial layer and the silicon substrate to form a recessed area separating source and drain regions in the isolation region, the recessed area having a recess depth;

forming an epitaxial channel conformally in the recessed area;

forming a recessed gate over the epitaxial channel in the recessed area, the recessed gate including a gate dielectric having a high dielectric constant; and

forming metal quantum dots in the source and drain regions, the metal quantum dots having a crystalline structure that is different from a crystalline structure of the doped epitaxial layer, the metal quantum dots each having a top side planar with a top side of the silicon substrate.

16. The method of claim 15 wherein the doped epitaxial layer includes epitaxial doped with one or more of phosphorous, arsenic, or boron.

17. The method of claim 15 wherein growing a doped epitaxial layer includes incorporating dopants in-situ during epitaxial crystal growth to a dopant concentration within a range of about 1.0 E19-1.0 E21 atoms/cm³.

18. The method of claim 15 wherein the doped epitaxial layer has a uniform, horizontal doping profile.

19. The method of claim 15 wherein the recess depth coincides with a boundary between the doped epitaxial layer and the silicon substrate.