JFET and method of manufacturing thereof
First Claim
1. A vertical JFET, comprising:
- a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface;
a source metallization arranged on the first surface;
a drain metallization arranged on the second surface; and
a gate metallization arranged on the first surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises;
an n-doped first semiconductor region in ohmic contact with the drain metallization and the source metallization;
a plurality of p-doped second semiconductor regions in ohmic contact with the gate metallization, substantially extending to the first surface, spaced apart from one another and forming respective first pn-junctions with the first semiconductor region; and
a plurality of p-doped body regions in ohmic contact with the source metallization, spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and forming respective second pn-junctions with the first semiconductor region,wherein the semiconductor body further comprises at least one conductive plug extending from the source metallization to one of the body regions.
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Accused Products
Abstract
A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.
10 Citations
14 Claims
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1. A vertical JFET, comprising:
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a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface; a source metallization arranged on the first surface; a drain metallization arranged on the second surface; and a gate metallization arranged on the first surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises; an n-doped first semiconductor region in ohmic contact with the drain metallization and the source metallization; a plurality of p-doped second semiconductor regions in ohmic contact with the gate metallization, substantially extending to the first surface, spaced apart from one another and forming respective first pn-junctions with the first semiconductor region; and a plurality of p-doped body regions in ohmic contact with the source metallization, spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and forming respective second pn-junctions with the first semiconductor region, wherein the semiconductor body further comprises at least one conductive plug extending from the source metallization to one of the body regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A JFET, comprising:
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a semiconductor body comprising a semiconductor material that has a band-gap higher than about two electron volts and extends between a first surface and a second surface which runs substantially parallel to the first surface; a source metallization arranged on the first surface; a gate metallization arranged on the first surface; and a drain metallization arranged on the second surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises; a first semiconductor region in ohmic contact with the source metallization and the drain metallization; at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region; and at least one body region completely embedded in the first semiconductor region and forming a second pn-junction with the first semiconductor region, wherein the at least one body region is spaced apart from the first surface and from the source metallization, wherein at least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions, and wherein the semiconductor body further comprises in the sectional plane a plurality of second semiconductor regions forming a first lattice and a plurality of body regions forming a second lattice. - View Dependent Claims (12, 13, 14)
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Specification