Front-side emitting mid-infrared light emitting diode fabrication methods

• US 9,711,679 B2
• Filed: 03/11/2015
• Issued: 07/18/2017
• Est. Priority Date: 03/11/2014
• Status: Active Grant

• Current Assignee: Terahertz Device Corporation
• Original Assignee: Terahertz Device Corporation
• Inventors: Miller, Mark S.
• Primary Examiner(s): Cao, Phat X
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/645,025
• Publication Number:
  US 20150263218A1
• Time in Patent Office: 860 Days
• Field of Search: 438 27
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 33/0062 for devices with an active region comprising only III-V compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

Methods for fabricating mid-infrared light emitting diodes (LEDs) based upon antimonide-arsenide semiconductor heterostructures and configured into front-side emitting high-brightness LED die and other LED die formats.

Claims

1. A method for manufacturing a mid-infrared LED, the method comprising:

forming an electrical contact between a substrate and a first light emission stage using variable-period superlattices;

forming first and subsequent light emission stages to have double-heterostructure confinement configurations, with variable period semiconductor superlattices forming one or more charge injectors and minority carrier barriers;

forming cascaded light emission stages by forming semi-metallic tunneling junctions between light emission stages using a junction between layers of GaSb and InAs doped with Si on both sides of the junction;

growing strain-balanced superlattices and heterostructures;

forming an electrical contact between a topmost light emission stage and an InAs current-spreading and ohmic contact layer using variable-period superlattices; and

growing a layer of GaSb for etching light-extraction surface features.

2. The method of claim 1 further comprising growing light emission layers comprised of superlattice structures, where the thicknesses of the superlattice layers are adjusted to determine the light emission wavelength.

3. The method of claim 1 further comprising growing light emission layers comprised of quantum well structures, where the thicknesses of the quantum well and barrier layers are adjusted to determine the light emission wavelength.

4. The method of claim 1 further comprising:

etching light extraction surface features and electrical contact vias to an InAs current spreading layer into a topmost layer of GaSb;

defining a geometry of weakly-coupled surface buttes using photolithography, with butte size and spacing adjusted to accommodate efficient light extraction at wavelengths of one or more light emission layers;

etching through most of a topmost epitaxial layer of GaSb using a dry plasma-based etch with a Cl-based etch gas mixture; and

completing the etch through a last portion of an epitaxial layer of GaSb using a chemically-selective wet etch based upon an ammonium hydroxide solution chosen to selectively stop etching on the underlying InAs electrical contact layer.

5. The method of claim 1 further comprising:

etching light extraction surface features and electrical contact vias to an InAs current spreading layer into a topmost layer of GaSb;

completing the etch through a last portion of the epitaxial layer of GaSb using a chemically-selective wet etch based upon an ammonium hydroxide solution chosen to selectively stop etching on an underlying InAs electrical contact layer; and

optically or visually detecting an endpoint of the wet etch by observing an etching surface color change as final remnants of GaSb are etched from the surface to expose underlying InAs.

6. The method of claim 1 further comprising:

etching mesa and trench features through cascaded light emission stages to define and electrically isolate an active device area;

defining a geometry of the active device area using photolithography;

etching through cascaded active heterostructure layers using a dry plasma-based etch with a Cl-based etch gas mixture; and

etching dry-etched surfaces with hydrogen chloride or ammonium hydroxide based aqueous solutions to remove surface damage from dry etching.

7. The method of claim 1 further comprising:

defining a metal contact and wire bond pad geometries using photolithography;

depositing a sequence of metal layers on an exposed InAs current spreading layer that include an adhesion layer, a layer of Pt as an Au diffusion barrier, and a layer of Au that is thicker than the Pt layer for conducting current across the device and providing a wire bond pad metal; and

forming a final pattern by lifting off unwanted metal.

8. The method of claim 1 further comprising:

defining regions to not be covered with an anti-reflection coating using photolithography;

depositing a sequence of dielectric layers with compositions and thicknesses matched to operating wavelengths of the light emission superlattices; and

forming a final pattern by lifting off unwanted dielectric material.

9. The method of claim 1 further comprising:

defining regions to not be covered with surface passivation layers using photolithography;

treating one or more exposed heterostructure surfaces and other regions by etching a surface oxide with an aqueous solution;

depositing a sequence of layers to passivate a treated surface; and

forming a final pattern by either lifting off or etching unwanted passivation material.

10. The method of claim 1 further comprising:

defining regions to not be covered with surface passivation layers and an antireflection coating using photolithography;

treating exposed heterostructure surfaces and other regions by etching a surface oxide with an aqueous solution;

depositing a sequence of layers which both passivate a treated surface and provide for an antireflection coating; and

forming a final pattern by either lifting off or etching the unwanted passivation and antireflection material.

11. The method of claim 1 further comprising:

lapping or grinding a substrate to approximately 50 μ

m or less, and

polishing a surface of the substrate to give a smooth surface for forming an internally-reflecting mirror.

12. The method of claim 1 further comprising:

defining one or more coverage geometries using photolithography;

depositing a sequence of metal layers on an exposed GaSb substrate that include a layer of Pd for reacting with the GaSb to form an electrical contact, followed by a layer of Ti as a diffusion barrier for an intermetallic reaction layer barrier, a layer of Pt as an Au diffusion barrier;

depositing a further sequence of metal layers on a Pt surface that include a layer of Pt as an Au diffusion barrier, and a thicker layer of Au for conducting current;

depositing a further sequence of metal layers on an Au surface that include a layer of Ni as a eutectic reaction barrier and a thicker layer of metal or metal alloy for forming a eutectic die attach packaging bond;

forming a final pattern by lifting off unwanted metal; and

annealing deposited metals to complete a Pd—

GaSb reaction.

13. The method of claim 1 further comprising:

attaching a die to a package using an Au;

Sn eutectic solder or a conducting epoxy; and

bonding at least one top bonding pad with at least one bonding wire.

20. The method of claim 1, wherein growing a layer of GaSb includes growing alloys of GaSb.

14. A method to manufacture mid-infrared LED, the method comprising:

defining geometry of weakly-coupled surface buttes using photolithography, with a butte size and a butte spacing adjusted to accommodate efficient light extraction at one or more wavelengths of the light emission layers;

etching through most of a topmost epitaxial layer of GaSb using a dry plasma-based etch with a Cl-based etch gas mixture; and

completing an etch through a last portion of the topmost epitaxial layer of GaSb using a chemically-selective wet etch based upon an ammonium hydroxide solution chosen to selectively stop etching on an underlying InAs electrical contact layer;

defining one or more coverage geometries using photolithography;

depositing a sequence of metal layers on an exposed GaSb substrate that include a layer of Pd for reacting with GaSb to form an electrical contact, followed by a layer of Ti as a diffusion barrier for an intermetallic reaction layer barrier, a layer of Pt as a Au diffusion barrier;

depositing a further sequence of metal layers on a Pt surface that include a layer of Pt as an Au diffusion barrier and a thicker layer of Au for conducting current;

depositing a further sequence of metal layers on an Au surface that include a layer of Ni as a eutectic reaction barrier and a thicker layer of metal or metal alloy for forming a eutectic die attach packaging bond;

forming a final pattern by lifting off unwanted metal; and

annealing deposited metals to complete a Pd—

GaSb reaction.

15. The method as recited in claim 14, further comprising:

defining a metal contact and wire bond pad geometries using photolithography;

depositing a sequence of metal layers on an exposed InAs current spreading layer that include an adhesion layer, such as Ti, a layer of Pt as an Au diffusion barrier, and a layer of Au that is thicker than the Pt layer for conducting current across the LED and providing a wire bond pad metal; and

forming a final pattern by lifting off unwanted metal.

16. The method as recited in claim 14, further comprising:

defining regions to not be covered with an anti-reflection coating using photolithography;

depositing a sequence of dielectric layers with compositions and thicknesses matched to one or more operating wavelengths of one or more light emission superlattices; and

forming a final pattern by lifting off unwanted dielectric material.

17. The method as recited in claim 14, further comprising:

defining regions to not be covered with surface passivation layers using photolithography;

treating one or more exposed heterostructure surfaces and other regions by etching a surface oxide with an aqueous solution;

depositing a sequence of layers to passivate a treated surface; and

forming a final pattern by either lifting off or etching unwanted passivation material.

18. The method as recited in claim 14, further comprising:

lapping or grinding at least a portion of a substrate to approximately 50 μ

m or less, and

polishing a surface of the at least a portion of the substrate to give a smooth surface for forming an internally-reflecting mirror.

19. A method for fabricating a device emitting mid-infrared light, the method comprising:

growing epitaxial crystalline semiconductor device layers by molecular beam epitaxy on a front surface of a semiconductor substrate of GaSb wherein the layers are comprised of InAs, GaAs, or AlSb;

forming strain-balanced heterostructures during molecular beam epitaxial growth that comprise light emitting structures cascaded by tunnel junctions;

lithographically etching dielectric light output coupling surface structures into a topmost GaSb epitaxial layer;

lithographically etching mesas and trenches through the heterostructure layers to define and isolate an active regions of the device;

depositing and lithographically patterning a current-spreading front-surface metal electrical contact structure;

depositing and lithographically patterning a front-side anti-reflection coating on one or more light extraction surface features;

etching surfaces of the heterostructure sidewalls and depositing a chemical and electrical passivation coating;

removing at least some amount of the substrate, to decrease light absorption and increase thermal conduction, and polishing a backside of the substrate for forming a backside internal mirror;

depositing backside metals that form an internal mirror, an electrical contact, and a surface layer for eutectic die attachment; and

attaching a finished die to a light emitting diode package with eutectic solder or conducting epoxy and wire bonding to at least one frontside device bond pad.