High speed tri-level input power converter gate driver

• US 9,712,058 B1
• Filed: 08/29/2016
• Issued: 07/18/2017
• Est. Priority Date: 08/29/2016
• Status: Active Grant

• Current Assignee: Silanna Asia Pte. Ltd.
• Original Assignee: Silanna Asia Pte. Ltd.
• Inventors: Newlin, Trevor M.
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Tiku, Sisay G
• Application Number:
  US15/250,531
• Time in Patent Office: 323 Days
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various methods and devices that involve electronic circuits are disclosed. A disclosed method includes buffering an input signal using a first buffer. The first buffer is powered by a supply voltage and a reference voltage. The method also includes buffering the input signal using a second buffer. The second buffer is powered by the reference voltage and a ground voltage. The method also includes level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, and level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter. The voltage range is larger than a delta between the supply voltage and the reference voltage. The reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage.

Claims

1. A control circuit comprising:

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output and the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage;

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

a reference voltage generator coupled to the supply voltage and the ground voltage;

an impedance divider in the reference voltage generator that generates the reference voltage from the supply voltage; and

a reference voltage generator capacitor coupled between the reference voltage and the ground voltage, wherein the reference voltage generator capacitor is at least 1.5 picofarads.

2. The control circuit of claim 1, wherein:

the first level shifter is powered by the supply voltage and the ground voltage; and

the second level shifter is powered by the supply voltage and the ground voltage.

3. The control circuit of claim 2, wherein the first and second level shifters each individually comprise:

a first circuit branch coupled between the supply voltage and the ground voltage;

a first field effect transistor located on the first circuit branch and having a first control gate;

a second circuit branch coupled between the supply voltage and the ground voltage;

a second field effect transistor located on the second circuit branch and having a second control gate; and

an internal inverter having an internal inverter input coupled to the first control gate and an internal inverter output coupled to the second control gate.

4. The control circuit of claim 1, further comprising:

a common control circuit input, wherein the common control circuit input is coupled to the first input and the second input;

a high side control circuit output, wherein an output of the first level shifter is the high side control circuit output; and

a low side control circuit output, wherein an output of the second level shifter is the low side control circuit output.

5. The control circuit of claim 4, further comprising:

a logic circuit communicatively coupled to the high side control circuit output and the low side control circuit output; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the logic circuit output is true when the high side control circuit output and the low side control circuit output are both false.

6. The control circuit of claim 4, further comprising:

a logic circuit communicatively coupled to the high side control circuit output and the low side control circuit output; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the trilevel output signal is true when the common control circuit input equals the reference voltage.

7. The control circuit of claim 6, further comprising:

a delay circuit coupled to the logic circuit output;

wherein a delay of the delay circuit is at least 5 nanoseconds.

8. A power converter comprising:

a control loop that regulates an output of the power converter using a switching circuit, wherein the switching circuit is coupled between an input side of the power converter and a load side of the power converter;

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output and the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage; and

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

wherein the first level shifter and the second level shifter are on the control loop;

wherein the switching circuit further comprises a high side power field effect transistor with a high side gate node, and a low side power field effect transistor with a low side gate node;

wherein the high side power field effect transistor is coupled to the input side of the power converter and the low side power field effect transistor, the low side power field effect transistor is coupled to the high side power field effect transistor and a power ground voltage, the first level shifter produces a high side drive signal for the high side gate node, and the second level shifter produces a low side drive signal for the low side gate node;

wherein the power converter further comprises a reference voltage generator coupled between the supply voltage and the ground voltage, an impedance divider in the reference voltage generator that generates the reference voltage from the supply voltage, and a reference voltage generator capacitor coupled between the reference voltage and the ground voltage, wherein the reference voltage generator capacitor is at least 1.5 picofarads.

9. The power converter of claim 8, further comprising:

the first level shifter is powered by the supply voltage and the ground voltage; and

the second level shifter is powered by the supply voltage and the ground voltage.

10. The power converter of claim 8, further comprising:

a high side gate driver circuit powered by a boosted voltage supply, and coupled to the high side gate node, wherein the high side gate driver drives the high side power field effect transistor using the high side drive signal;

a low side gate driver circuit biased by the power ground voltage, and coupled to the low side gate node, wherein the low side gate driver drives the low side power field effect transistor using the low side drive signal;

a high side latch communicatively coupled to the high side gate driver and the first level shifter, wherein the high side latch latches the high side drive signal; and

a low side latch communicatively coupled to the low side gate driver and the second level shifter, wherein the low side latch latches the low side drive signal.

11. The power converter of claim 8, further comprising:

a common control circuit input on the control loop, wherein the common control circuit input is coupled to the first input and the second input;

wherein the high side drive signal and the low side drive signal are both based on a first pulse width modulated signal received on the common control circuit input; and

wherein the high side drive signal and the low side drive signal are second and third pulse width modulated signals.

12. The power converter of claim 11, wherein:

a logic circuit communicatively coupled to the first level shifter and the second level shifter; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the high side power field effect transistor and the low side power field effect transistor are both turned off when the logic circuit output is true.

13. The power converter of claim 11, further comprising:

a logic circuit communicatively coupled to the first level shifter and the second level shifter; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal;

wherein the trilevel output signal is true when the common control circuit input equals the reference voltage.

14. The power converter of claim 13, further comprising:

a delay circuit coupled to the logic circuit output;

wherein a delay of the delay circuit is at least 5 nanoseconds; and

wherein an output of the delay circuit turns both the high side power field effect transistor and the low side power field effect transistor off.

15. The power converter of claim 11, wherein the first and second level shifters each individually comprise:

a first circuit branch coupled between the supply voltage and the ground voltage;

a first field effect transistor located on the first circuit branch and having a first control gate;

a second circuit branch coupled between the supply voltage and the ground voltage;

a second field effect transistor located on the second circuit branch and having a second control gate; and

an internal inverter having an internal inverter input coupled to the first control gate and an internal inverter output coupled to the second control gate.

16. A method comprising:

buffering an input signal using a first buffer, wherein the first buffer is powered by a supply voltage and a reference voltage, wherein the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

buffering the input signal using a second buffer, wherein the second buffer is powered by the reference voltage and a ground voltage;

level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage;

level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter;

regulating a load using a high side power field effect transistor, a low side power field effect transistor, and a control loop, wherein the input signal is on the control loop;

generating a high side drive signal via at least the level shifting of the first buffer output signal;

generating a low side drive signal via at least the level shifting of the second buffer output signal;

driving the high side power field effect transistor using the high side drive signal; and

driving the low side power field effect transistor using the low side drive signal;

generating a logic circuit output using a logic circuit, wherein the logic circuit is communicatively coupled to the first level shifter and the second level shifter;

delaying the logic circuit output using a delay circuit with a delay of at least 5 nanoseconds to produce a delayed logic circuit output;

generating a trilevel output signal if the delayed logic circuit output stays true for greater than 5 nanoseconds;

altering a characteristic of the control loop using the trilevel output signal;

generating the reference voltage from the supply voltage using a reference voltage generator; and

supplying power to the second buffer using a reference voltage generator capacitor, wherein the reference voltage generator capacitor is at least 1.5 picofarads.

17. A control circuit comprising:

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output and the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage; and

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

a common control circuit input, wherein the common control circuit input is coupled to the first input and the second input;

a high side control circuit output, wherein an output of the first level shifter is the high side control circuit output; and

a low side control circuit output, wherein an output of the second level shifter is the low side control circuit output;

a logic circuit communicatively coupled to the high side control circuit output and the low side control circuit output; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal, wherein the trilevel output signal is true when the common control circuit input equals the reference voltage.

18. The control circuit of claim 17, further comprising:

a delay circuit coupled to the logic circuit output;

wherein a delay of the delay circuit is at least 5 nanoseconds.

19. A power converter comprising:

a control loop that regulates an output of the power converter using a switching circuit, wherein the switching circuit is coupled between an input side of the power converter and a load side of the power converter;

a first buffer powered by a supply voltage and a reference voltage, wherein the first buffer buffers a first input on a first output and the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

a second buffer powered by the reference voltage and a ground voltage, wherein the second buffer buffers a second input on a second output;

a first level shifter, wherein the first level shifter shifts the first output to a voltage range, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage;

a second level shifter, wherein the second level shifter shifts the second output to the voltage range;

wherein the first level shifter and the second level shifter are on the control loop;

a high side power field effect transistor with a high side gate node;

a low side power field effect transistor with a low side gate node;

wherein the high side power field effect transistor is coupled to the input side of the power converter and the low side power field effect transistor;

wherein the low side power field effect transistor is coupled to the high side power field effect transistor and a power ground voltage;

wherein the first level shifter produces a high side drive signal for the high side gate node;

wherein the second level shifter produces a low side drive signal for the low side gate node;

a common control circuit input on the control loop, wherein the common control circuit input is coupled to the first input and the second input, wherein the high side drive signal and the low side drive signal are both based on a first pulse width modulated signal received on the common control circuit input, and the high side drive signal and the low side drive signal are second and third pulse width modulated signals;

a logic circuit communicatively coupled to the first level shifter and the second level shifter; and

a logic circuit output of the logic circuit that is used to produce a trilevel output signal, wherein the trilevel output signal is true when the common control circuit input equals the reference voltage.

20. The power converter of claim 19, further comprising:

a delay circuit coupled to the logic circuit output;

wherein a delay of the delay circuit is at least 5 nanoseconds; and

wherein an output of the delay circuit turns both the high side power field effect transistor and the low side power field effect transistor off.

21. A method comprising:

buffering an input signal from a common control circuit using a first buffer, wherein the first buffer is powered by a supply voltage and a reference voltage, wherein the reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage;

buffering the input signal using a second buffer, wherein the second buffer is powered by the reference voltage and a ground voltage;

level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, wherein the voltage range is larger than a delta between the supply voltage and the reference voltage, and the level-shifted first buffer output signal is a high side control circuit output;

level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter, wherein the level-shifted second buffer output signal is a low side control circuit output;

generating a logic circuit output from the high side control circuit output and the low side control circuit output; and

producing a trilevel output signal from the logic circuit output, wherein the trilevel output signal is true when the common control circuit input equals the reference voltage.

22. The method of claim 21, further comprising:

delaying the trilevel output signal from the logic circuit output at least 5 nanoseconds.