Digital readout method and apparatus

• US 9,712,771 B2
• Filed: 06/09/2016
• Issued: 07/18/2017
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Kelly, Michael, Mooney, Daniel, Colonero, Curtis, Berger, Robert, Candell, Lawrence
• Primary Examiner(s): Jean Pierre, Peguy
• Application Number:
  US15/178,439
• Publication Number:
  US 20160295151A1
• Time in Patent Office: 404 Days
• Field of Search: 341144, 341161, 341163, 341157, 341 15, 250214, 2502081
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array.

Claims

1. An apparatus comprising:

a sensor array comprising a sensor to generate a signal; and

an analog-to-digital converter (ADC) array comprising an ADC operably coupled to the sensor, the ADC comprising a capacitance to be charged by the signal, the capacitance defining a least significant bit (LSB) of the ADC,

wherein the sensor comprises an avalanche photodiode (APD) to charge the capacitance at a rate greater than a photon flux incident on the APD.

2. The apparatus of claim 1, wherein the capacitance has a value of about 1 femtofarad to about 10 femtofarads.

3. The apparatus of claim 1, wherein the capacitance is defined by a parasitic capacitance.

4. The apparatus of claim 1, further comprising:

an amplifier, operably coupled to the sensor, to amplify the signal generated by the sensor.

5. The apparatus of claim 4, wherein the amplifier comprises at least one of a direct injection amplifier, a buffered direct injection amplifier, a source follower amplifier, a transimpedance amplifier, or a current mirror.

6. The apparatus of claim 4, wherein the amplifier is disposed within a unit cell defined by the ADC.

7. The apparatus of claim 4, wherein the amplifier is disposed within an amplifier array operably coupled to the sensor array and the ADC array.

8. A method of analog-to-digital conversion, the method comprising:

generating an analog signal at a sensing element in a plurality of sensing elements;

transferring the analog signal from the sensing element to an analog-to-digital converter (ADC) in a plurality of analog-to-digital converters (ADCS); and

integrating the analog signal in a capacitance in the ADC, the capacitance defining a least significant bit (LSB) of the ADC.

9. The method of claim 8, wherein generating the analog signal comprises converting a photon flux into a photocurrent with an avalanche photodiode.

10. The method of claim 9, wherein integrating the analog signal in the capacitance occurs at a rate faster than the photon flux.

11. The method of claim 8, further comprising:

amplifying the analog signal before integrating the analog signal in the capacitance.

12. An apparatus comprising:

an avalanche photodiode (APD) array comprising a plurality of APDs; and

an analog-to-digital converter (ADC) array comprising a plurality of ADCs, each ADC in the plurality of ADCs operably coupled to a corresponding APD in the plurality of APDs and comprising a corresponding capacitance to be charged by photocurrent from the corresponding APD at a rate greater than a photon flux incident on the corresponding APD.

13. The apparatus of claim 12, wherein each ADC in the plurality of ADCs defines a corresponding unit cell having a dimension less than or equal to a pitch of the APD array.

14. The apparatus of claim 13, wherein each corresponding unit cell comprises a corresponding preamplifier, operably coupled to the corresponding APD, to amplify the photocurrent generated by the corresponding APD.

15. The apparatus of claim 14, wherein each corresponding preamplifier comprises at least one of a direct injection amplifier, a buffered direct injection amplifier, a source follower amplifier, a transimpedance amplifier, or a current mirror.

16. The apparatus of claim 12, wherein each corresponding capacitance is defined by a corresponding parasitic capacitance within the corresponding unit cell.

17. The apparatus of claim 12, wherein each corresponding capacitance defines a corresponding least significant bit (LSB) of the corresponding ADC.

18. The apparatus of claim 12, wherein each corresponding capacitance has a value of about 1 femtofarad to about 10 femtofarads.