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At-speed integrated circuit testing using through silicon in-circuit logic analysis

  • US 9,714,978 B2
  • Filed: 04/12/2013
  • Issued: 07/25/2017
  • Est. Priority Date: 04/12/2012
  • Status: Active Grant
First Claim
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1. A method for testing an integrated circuit, the method comprising:

  • selecting a plurality of areas of interest on the integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

    illuminating each of the areas of interest over a plurality of cycles;

    receiving a reflected signal from the illuminated areas of interest, wherein the reflected signal is modulated by at least one of voltage and current present within at least one of the electronic devices;

    converting the received reflected signal into an electrical signal;

    analyzing the electric signal to determine a bit pattern and timing information for one or more of the electronic devices; and

    comparing the bit patterns and timing information to a pre-determined bit pattern for the one or more electronic devices to determine one or more errors in one or more of the electronic devices.

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