At-speed integrated circuit testing using through silicon in-circuit logic analysis

• US 9,714,978 B2
• Filed: 04/12/2013
• Issued: 07/25/2017
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: Semicaps Pte Limited
• Original Assignee: Larry Ross, Michael Bruce
• Inventors: Ross, Larry, Bruce, Michael
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): RAJAPUTRA, SURESH KS
• Application Number:
  US13/862,244
• Publication Number:
  US 20140149811A1
• Time in Patent Office: 1,565 Days
• Field of Search: None
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.

Claims

1. A method for testing an integrated circuit, the method comprising:

selecting a plurality of areas of interest on the integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

illuminating each of the areas of interest over a plurality of cycles;

receiving a reflected signal from the illuminated areas of interest, wherein the reflected signal is modulated by at least one of voltage and current present within at least one of the electronic devices;

converting the received reflected signal into an electrical signal;

analyzing the electric signal to determine a bit pattern and timing information for one or more of the electronic devices; and

comparing the bit patterns and timing information to a pre-determined bit pattern for the one or more electronic devices to determine one or more errors in one or more of the electronic devices.

2. The method of claim 1, further comprising;

comparing the bit pattern and timing information to a pre-determined logic pattern to determine one or more errors in the electronic devices.

3. The method of claim 1, wherein the areas of interest are determined using CAD data that define scan boundaries for the instrument.

4. The method of claim 1, wherein successive areas of interest are not adjacent.

5. The method of claim 1, wherein the areas of interest are determined using user-supplied data.

6. The method of claim 1, wherein illuminating each of the areas of interest comprises positioning an XY stage.

7. The method of claim 1, further comprising:

successively illuminating and analyzing to determine a time-based logic pattern for one or more of the electronic devices.

8. The method of claim 7, further comprising displaying, using one or more display surfaces, the time-based logic pattern.

9. A system for testing an integrated circuit, comprising:

a laser for illuminating a plurality of areas of interest on the integrated circuit, wherein each of the areas of interest correspond to an electronic device of the integrated circuit;

a photodetector for receiving a reflected signal from the illuminated areas of interest and converting the received reflected signal into an electrical signal; and

a processor, the processor being adapted to execute a set of program code instructions, which when executed cause the processor to;

analyze the electric signal to determine a bit pattern and timing information for one or more of the electronic devices; and

compare the bit patterns and timing information to a pre-determined bit pattern for the one or more electronic devices to determine one or more errors in one or more of the electronic devices.

10. The system of claim 9, wherein the areas of interest are determined using CAD data that define scan boundaries for the instrument.

11. The system of claim 9, wherein successive areas of interest are not adjacent.

12. The system of claim 9, wherein the areas of interest are determined using user-supplied data.

13. The system of claim 9, further comprising:

an XY stage for positioning the integrated circuit so that the areas of interest may be illuminated by the laser.

14. The system of claim 9, wherein the processor is further configured to determine a time-based logic pattern for one or more of the electronic devices.

15. The system of claim 14, wherein the processor is further configured to provide a display of the time-based logic pattern.

16. A computer program product embodied in a non-transitory computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a process for testing an integrated circuit, the process comprising:

selecting a plurality of areas of interest on the integrated circuit that correspond to a plurality of electronic devices of the integrated circuit;

illuminating each of the areas of interest over a plurality of cycles;

receiving a reflected signal from the illuminated areas of interest, wherein the reflected signal is modulated by at least one of voltage and current present within at least one of the electronic devices;

converting the received reflected signal into an electrical signal;

analyzing the electric signal to determine a bit pattern and timing information for one or more of the electronic devices; and

comparing the bit patterns and timing information to a pre-determined bit pattern for the one or more electronic devices to determine one or more errors in one or more of the electronic devices.

17. The computer program product of claim 16, wherein the sequence of instructions further causes the processor to execute a process comprising:

determining a probability of a match of a bit pattern for an electronic device of the one or more electronic devices to the pre-determined logic pattern for the electronic device.

18. The computer program product of claim 16, wherein the areas of interest are determined using CAD data that define scan boundaries for the instrument.

19. The computer program product of claim 16, wherein the areas of interest are determined using user-supplied data.

20. The computer program product of claim 16, wherein successive areas of interest are not adjacent.

21. The computer program product of claim 16, wherein the sequence of instructions further cause the processor to execute a process comprising:

determining a time-based logic pattern.

22. The computer program product of claim 16, wherein the sequence of instructions further cause the processor to execute a process comprising:

determining at least one of a Schmoo plot and a graphical representation of selective test parameters.

23. The computer program product of claim 16, wherein the sequence of instructions further cause the processor to execute a process comprising;

cross referencing at least one of a logic cell chains or cones to correlate as passing or failing.

24. The computer program product of claim 16, wherein the sequence of instructions further cause the processor to execute a process comprising:

sampling Boolean logic for at least one of thresholding, box car averaging, and edge enhancement.

25. The computer program product of claim 16, wherein the sequence of instructions further cause the processor to execute a process comprising:

calculating a minimum number of areas of interest for determining a passing state for the integrated circuit.

26. A method for testing an integrated circuit, the method comprising:

selecting a plurality of areas of interest on an integrated circuit, each of the areas of interest corresponding to an electronic devices of the integrated circuit;

illuminating each of the areas of interest;

receiving a reflected signal from illumination of the areas of interest;

reflected signal is modulated by voltage or current in internal device of the integrated circuit;

detecting illumination with a photodetector and converting into an electrical signal

digitizing the electrical signal with a high acquisition speed digitizer.

27. The method of claim 26, wherein the high acquisition speed digitizer is configured to capture available loop trigger events, the method further comprising:

converting modulation into waveforms.

28. The method of claim 27, further converting waveforms from claim 27 into a bit pattern for comparison with a pre-determined bit pattern.