Circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator

• US 9,715,245 B2
• Filed: 01/20/2015
• Issued: 07/25/2017
• Est. Priority Date: 01/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Chen-Lun, Li, Gu-Huan, Chen, Chung-Chieh, Kuo, Cheng-Hsiung
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US14/600,076
• Publication Number:
  US 20160209854A1
• Time in Patent Office: 917 Days
• Field of Search: 327540, 327541, 327539
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G05F 3/267 using both bipolar and field-effect technology
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator are provided. A current source is configured to generate a reference current, and an error amplifier has a first input, a second input, and a single-ended output. The first input is connected to a reference voltage, and the second input is connected to an output node of the circuit via a feedback resistor. A pass transistor includes a control electrode connected to the single-ended output of the error amplifier, a first electrode connected to a power supply voltage, and a second electrode connected to the output node of the circuit. A first branch of a current mirror is connected to the current source, and a second branch of the current mirror is connected to the second terminal of the feedback resistor. The output node provides an output voltage of the circuit.

Claims

1. A circuit for generating an output voltage that is substantially constant despite process, voltage, or temperature variation in the circuit, the circuit comprising:

an error amplifier having a first input, a second input, and a single-ended output, wherein the first input is electrically connected to a reference voltage, and the second input is electrically connected to an output node of the circuit via a feedback resistor, the feedback resistor including a first terminal electrically connected to the output node and a second terminal electrically connected to the second input;

a pass transistor including a control electrode electrically connected to the single-ended output of the error amplifier, a first electrode electrically connected to a power supply voltage, and a second electrode electrically connected to the output node of the circuit;

a current source configured to generate a reference current that changes when a resistance of the feedback resistor changes;

a first branch of a current mirror electrically connected to the current source, the reference current flowing through the first branch; and

a second branch of the current mirror electrically connected to the second terminal of the feedback resistor, wherein an output current that flows through the second branch and between the first and second terminals of the feedback resistor is based on (i) the reference current flowing through the first branch, and (ii) a mirror ratio of the current mirror,

wherein the output node provides an output voltage of the circuit, and the current source includes;

a complementary metal-oxide-semiconductor (CMOS) operational amplifier including a first input, a second input, and a single-ended output, wherein the first input of the CMOS operational amplifier is electrically connected to the reference voltage,

a first PMOS transistor having a source terminal electrically connected to the power supply voltage, and a gate terminal electrically connected to the single-ended output of the CMOS operational amplifier,

a first resistor having a first terminal electrically connected to a drain terminal of the first PMOS transistor, and a second terminal electrically connected to the second input of the CMOS operational amplifier,

a second resistor having a first terminal electrically connected to the second terminal of the first resistor, and a second terminal electrically connected to a ground reference voltage, and

a second PMOS transistor having a source terminal electrically connected to the power supply voltage, a gate terminal electrically connected to the gate terminal of the first PMOS transistor, and a drain terminal electrically connected to the first branch of the current mirror.

2. The circuit of claim 1, wherein the output voltage is

V_OUT=V_REF+(R_FB*I_OUT),

where V_OUT is the output voltage, V_REF is the reference voltage, R_FB is the resistance of the feedback resistor, and I_OUT is the output current.

3. The circuit of claim 1, wherein the output voltage is based on the mirror ratio of the current mirror, the mirror ratio being a ratio between a current flowing through the first branch and a current flowing through the second branch.

4. The circuit of claim 3, wherein one or more parameters of the first or second branch of the current mirror are adjustable, and wherein the adjusting of the one or more parameters changes the mirror ratio and the output voltage of the circuit.

5. The circuit of claim 3, wherein the current mirror includes:

a switch configured to adjust the mirror ratio of the current mirror, wherein opening the switch causes the current mirror to have a first mirror ratio, and wherein closing the switch causes the current mirror to have a second mirror ratio, the opening and closing of the switch causing the output voltage of the circuit to change.

6. The circuit of claim 1,

wherein the first branch of the current mirror includes first one or more transistors, and

wherein the second branch of the current mirror includes second one or more transistors, the mirror ratio being based on (i) physical dimensions of the transistors included in the first and second branches, and (ii) a number of transistors included in each of the first and second branches.

7. The circuit of claim 1, wherein

the reference current varies based on process and temperature variation in the circuit,

the second resistor has a resistance R_REF,

the reference current is inversely proportional to the resistance R_REF, and

the resistance R_REF tracks changes in the resistance R_FB of the feedback resistor, the resistance R_REF increasing with increases in the resistance R_FB, and the resistance R_REF decreasing with decreases in the resistance R_FB.

8. The circuit of claim 7, wherein the feedback resistor and the second resistor are formed of a same material on a single substrate, such that the feedback resistor and the second resistor have similar electrical properties under process, voltage, and temperature (PVT) variation.

9. The circuit of claim 1, wherein the reference current tracks changes in the resistance R_FB of the feedback resistor, the reference current increasing with decreases in the resistance R_FB, and the reference current decreasing with increases in the resistance R_FB.

10. The circuit of claim 9, wherein

the second resistor has a resistance R_REF,

the reference current is inversely proportional to the resistance R_REF,

the resistance R_REF tracks the changes in the resistance R_FB of the feedback resistor, the resistance R_REF increasing with the increases in the resistance R_FB, and the resistance R_REF decreasing with the decreases in the resistance R_FB, and

the reference current tracks the changes in the resistance R_FB based on changes in the resistance R_REF.

11. The circuit of claim 9, wherein the changes in the resistance R_FB of the feedback resistor are a result of process, voltage, or temperature variation in the circuit.

12. The circuit of claim 11, wherein the output voltage of the circuit is

V_OUT=V_REF|(R_FB*α

*I_REF),

where V_OUT is the output voltage, V_REF is the reference voltage, α

is a constant based on the mirror ratio, and I_REF is the reference current,

wherein the reference current'"'"'s tracking of the changes in the resistance R_FB causes the output voltage to be substantially constant despite the process, voltage, or temperature variation in the circuit.

13. The circuit of claim 1, wherein the current source is a current-mode bandgap reference circuit.

14. The circuit of claim 1 comprising:

a voltage-mode bandgap reference circuit configured to generate the reference voltage.

15. The circuit of claim 1,

wherein the first branch of the current mirror includes:

a first NMOS transistor having a drain terminal electrically connected to the current source, and a gate terminal electrically connected to a bias voltage, and

a second NMOS transistor having a drain terminal electrically connected to a source terminal of the first NMOS transistor, and a source terminal electrically connected to a ground reference voltage;

wherein the second branch of the current mirror includes;

a third NMOS transistor having a drain terminal electrically connected to the second terminal of the feedback resistor, and a gate terminal electrically connected to the bias voltage,

a fourth NMOS transistor having a drain terminal electrically connected to a source terminal of the third NMOS transistor, a gate terminal electrically connected to a gate terminal of the second NMOS transistor, and a source terminal electrically connected to the ground reference voltage,

a fifth NMOS transistor having a drain terminal electrically connected to the second terminal of the feedback resistor, and a gate terminal electrically connected to the bias voltage, and

a sixth NMOS transistor having a drain terminal electrically connected to a source terminal of the fifth NMOS transistor, a gate terminal electrically connected to the gate terminal of the second NMOS transistor, and a source terminal electrically connected to the ground reference voltage via a switch.

17. The circuit of claim 1, wherein

as the resistance of the feedback resistor increases, the reference current decreases a corresponding amount that causes the output voltage to be substantially constant.

18. The circuit of claim 1, wherein the output voltage is substantially constant despite process, voltage, or temperature variation in the circuit.

16. A circuit for generating an output voltage that is substantially constant despite process, voltage, or temperature variation in the circuit, the circuit comprising:

an error amplifier having a first input, a second input, and a single-ended output, wherein the first input is electrically connected to a reference voltage, and the second input is electrically connected to an output node of the circuit via a feedback resistor, the feedback resistor including a first terminal electrically connected to the output node and a second terminal electrically connected to the second input;

a pass transistor including a control electrode electrically connected to the single-ended output of the error amplifier, a first electrode electrically connected to the power supply voltage, and a second electrode electrically connected to the output node of the circuit;

a current source configured to generate a reference current that changes when a resistance of the feedback resistor changes;

a current mirror including;

a first NMOS transistor including a source terminal electrically connected to a ground reference voltage, a gate terminal electrically connected to a drain terminal of the first NMOS transistor, and the drain terminal electrically connected to the current-mode bandgap reference circuit, wherein the reference current flows between the drain and source terminals of the first NMOS transistor, and

a second NMOS transistor including a source terminal electrically connected to the ground reference voltage, a gate terminal electrically connected to the gate terminal of the first NMOS transistor, and a drain terminal electrically connected to the second terminal of the feedback resistor,

wherein an output current that flows between the drain and source terminals of the second NMOS transistor is based on the reference current and a mirror ratio of the current mirror,

wherein the output node provides an output voltage of the circuit, and the current source includes;

a complementary metal-oxide-semiconductor (CMOS) operational amplifier including a first input, a second input, and a single-ended output, wherein the first input of the CMOS operational amplifier is electrically connected to the reference voltage,

a first PMOS transistor having a source terminal electrically connected to the power supply voltage, and a gate terminal electrically connected to the single-ended output of the CMOS operational amplifier,

a first resistor having a first terminal electrically connected to a drain terminal of the first PMOS transistor, and a second terminal electrically connected to the second input of the CMOS operational amplifier,

a second resistor having a first terminal electrically connected to the second terminal of the first resistor, and a second terminal electrically connected to a ground reference voltage, and

a second PMOS transistor having a source terminal electrically connected to the power supply voltage, a gate terminal electrically connected to the gate terminal of the first PMOS transistor, and a drain terminal electrically connected to the first branch of the current mirror.

19. The circuit of claim 16, wherein

as the resistance of the feedback resistor increases, the reference current decreases a corresponding amount that causes the output voltage to be substantially constant.

20. A circuit for generating an output voltage that is substantially constant despite process, voltage, or temperature variation in the circuit, the circuit comprising:

an error amplifier having a first input, a second input, and an output, wherein the first input is electrically connected to a reference voltage, and the second input is electrically connected to an output node of the circuit via a feedback resistor, the feedback resistor including a first terminal electrically connected to the output node and a second terminal electrically connected to the second input;

a pass transistor including a control electrode electrically connected to the output of the error amplifier, a first electrode electrically connected to a power supply voltage, and a second electrode electrically connected to the output node of the circuit;

a current source configured to generate a reference current that changes when a resistance of the feedback resistor changes;

a first branch of a current mirror electrically connected to the current source, the reference current flowing through the first branch; and

a second branch of the current mirror electrically connected to the second terminal of the feedback resistor, wherein an output current that flows through the second branch and between the first and second terminals of the feedback resistor is based on (i) the reference current flowing through the first branch, and (ii) a mirror ratio of the current mirror,

wherein the output node provides an output voltage of the circuit, and the current source includes;

an operational amplifier including a first input, a second input, and a single-ended output, wherein the first input of the operational amplifier is electrically connected to the reference voltage,

a first PMOS transistor having a source terminal electrically connected to the power supply voltage, and a gate terminal electrically connected to the single-ended output of the operational amplifier,

a first resistor having a first terminal electrically connected to a drain terminal of the first PMOS transistor, and a second terminal electrically connected to the second input of the operational amplifier,

a second resistor having a first terminal electrically connected to the second terminal of the first resistor, and a second terminal electrically connected to a ground reference voltage, and

a second PMOS transistor having a source terminal electrically connected to the power supply voltage, a gate terminal electrically connected to the gate terminal of the first PMOS transistor, and a drain terminal electrically connected to the first branch of the current mirror.