Regular via pattern for sensor-based input device

• US 9,715,304 B2
• Filed: 06/30/2015
• Issued: 07/25/2017
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Berget, Damien, Reynolds, Joseph Kurth, Morein, Stephen L.
• Primary Examiner(s): Shankar, Vijay
• Application Number:
  US14/788,575
• Publication Number:
  US 20170003791A1
• Time in Patent Office: 756 Days
• Field of Search: 345173-178
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

This disclosure generally describes an input device, a display device having an integrated capacitive sensing device, and an assembly for an input device. The input device comprises a plurality of sensor electrodes disposed in a first layer, and a processing system configured to detect presence of input objects in a sensing region defined proximate to the plurality of sensor electrodes. The input device further comprises a plurality of routing traces disposed in a second layer and coupled with the processing system, and a plurality of vias arranged in a regular pattern within an areal extent of the sensing region, wherein at least a portion of the plurality of vias couple the plurality of sensor electrodes with the plurality of routing traces.

Claims

1. An input device comprising:

a plurality of sensor electrodes disposed in a first layer, a sensing region defined proximate to the plurality of sensor electrodes;

a processing system configured to detect presence of input objects in the sensing region;

a plurality of routing traces disposed in a second layer and coupled with the processing system; and

a plurality of vias arranged in a regular pattern within an areal extent of the sensing region, wherein at least a portion of the plurality of vias couple the plurality of sensor electrodes with the plurality of routing traces.

2. The input device of claim 1, further comprising:

a plurality of source lines disposed in a layer outside the second layer and configured to be driven to perform display updating,

wherein at least a first routing trace of the plurality of routing traces is routed across at least one of the plurality of source lines.

3. The input device of claim 2, further comprising:

a display device including the plurality of source lines, the processing system coupled with the plurality of source lines and further configured for performing display updating,

wherein at least a second routing trace of the plurality of routing traces is disposed parallel to at least one of the plurality of source lines.

4. The input device of claim 1, further comprising:

a grid electrode disposed in the first layer and at least partly disposed between two of the plurality of sensor electrodes,

wherein the grid electrode is coupled with the processing system through one of the plurality of vias and one of the plurality of routing traces.

5. The input device of claim 1, wherein the plurality of sensor electrodes are disposed in a matrix configuration having a plurality of rows and a plurality of columns, wherein sensor electrodes disposed in a same row are each coupled with a respective via disposed in a same location relative to the sensor electrode.

6. The input device of claim 1, wherein the plurality of vias includes a plurality of dummy vias that are not coupled with the plurality of routing traces.

7. The input device of claim 6, further comprising a plurality of dummy traces disposed in parallel with the plurality of routing traces and that are not coupled with the processing system, wherein at least one of the plurality of dummy vias is coupled with at least one of the plurality of dummy traces.

8. A display device having an integrated capacitive sensing device, the display device comprising:

a plurality of source lines configured to perform display updating;

a plurality of routing traces, at least one of the plurality of routing traces being disposed parallel to at least one of the plurality of source lines;

a plurality of sensor electrodes configured to perform capacitive sensing of input objects in a sensing region defined proximate to the plurality of sensor electrodes, each sensor electrode corresponding to one or more segments of a common voltage electrode; and

a plurality of vias arranged in a regular pattern with an areal extent of the sensing region, wherein at least a portion of the plurality of vias couple the plurality of sensor electrodes with the plurality of routing traces.

9. The display device of claim 8, wherein the plurality of routing traces are disposed in a first layer and the plurality of source lines are disposed in a second layer,

wherein at least one of the plurality of routing traces is routed across at least one of the plurality of source lines.

10. The display device of claim 8, further comprising a grid electrode disposed at least partly between two of the plurality of sensor electrodes, the grid electrode corresponding to one or more segments of the common voltage electrode and coupled with one of the plurality of routing traces through one of the plurality of vias.

11. The display device of claim 8, wherein the plurality of sensor electrodes are disposed in a matrix configuration having a plurality of rows and a plurality of columns, wherein sensor electrodes disposed in a same row are each coupled with a respective via disposed in a same location relative to the sensor electrode.

12. The display device of claim 8, wherein the plurality of vias includes a plurality of dummy vias that are not coupled with the plurality of routing traces.

13. The display device of claim 12, further comprising a plurality of dummy traces disposed in parallel with the plurality of routing traces and that are not coupled with the processing system, wherein at least one of the plurality of dummy vias is coupled with at least one of the plurality of dummy traces.

14. An assembly for an input device, the assembly comprising:

a plurality of sensor electrodes disposed in a first layer and arranged to define a sensing region;

a plurality of routing traces disposed in a second layer and configured to couple with a processing system; and

a plurality of vias arranged in a regular pattern within an areal extent of the sensing region, wherein at least a portion of the plurality of vias couple the plurality of sensor electrodes with the plurality of routing traces.

15. The assembly of claim 14, further comprising:

a plurality of source lines disposed in a layer outside the second layer and configured to couple with the processing system for performing display updating,

wherein at least a first routing trace of the plurality of routing traces is routed across at least one of the plurality of source lines.

16. The assembly of claim 15, wherein at least a second routing trace of the plurality of routing traces is disposed parallel to at least one of the plurality of source lines.

17. The assembly of claim 14, further comprising:

a grid electrode disposed in the first layer and at least partly disposed between two of the plurality of sensor electrodes,

wherein the grid electrode is configured to couple with the processing system through one of the plurality of vias and one of the plurality of routing traces.

18. The assembly of claim 14, wherein the plurality of sensor electrodes are disposed in a matrix configuration having a plurality of rows and a plurality of columns, wherein sensor electrodes disposed in a same row are each coupled with a respective via disposed in a same location relative to the sensor electrode.

19. The assembly of claim 14, wherein the plurality of vias includes a plurality of dummy vias that are not coupled with the plurality of routing traces.

20. The assembly of claim 19, further comprising a plurality of dummy traces disposed in parallel with the plurality of routing traces, wherein at least one of the plurality of dummy vias is coupled with at least one of the plurality of dummy traces.