Method, apparatus and instructions for parallel data conversions

• US 9,715,384 B2
• Filed: 08/10/2016
• Issued: 07/25/2017
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanujam, Gopalan
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US15/233,482
• Publication Number:
  US 20160350111A1
• Time in Patent Office: 349 Days
• Field of Search: 708204, 708550-553
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1. A processor comprising:

a first register;

a decoder to decode an instruction;

a functional unit coupled with the decoder and the first register to convert, responsive to the instruction, a first format value comprising multiple sub-elements to a second format value comprising a same number of multiple sub-elements,

wherein the first format value sub-elements each are to have a first number of bits,

wherein each of the second format value sub-elements is to represent a number from a first format value sub-element with a second number of bits fewer than the first number of bits, and

wherein the functional unit is configured to store the second format value to an element of the first register.

2. The processor of claim 1, wherein the functional unit is to convert multiple first format values.

3. The processor of claim 2, wherein the multiple first format values are to be from a packed register of first format values.

4. The processor of claim 2, wherein the multiple first format values are to be from multiple registers of first format values.

5. The processor of claim 1, wherein the first format value represents a part of pixel data.

6. The processor of claim 1, wherein the first register is a 128-bit register, wherein the first number of bits is 8 bits, and wherein the second number of bits is 5 bits.

7. The processor of claim 1, wherein the second format value is stored to a lower half portion of the first register.

8. The processor of claim 1, wherein the second format value is stored to a higher half portion of the first register.

9. The processor of claim 1, wherein the first format value has at least 3 sub-elements.

10. A processor comprising:

a first register;

a decoder to decode an instruction;

a functional unit coupled with the decoder and the first register to convert, responsive to the instruction being decoded, a first format value from a second register to multiple second format values,

wherein the first format value is to have multiple sub-elements each to have a first number of bits,

wherein each of the second format values is to represent a number from a sub-element with a second number of bits greater than the first number of bits, and

wherein the functional unit is configured to store the multiple second format values to the first register.

11. The processor of claim 10, wherein the second register is a packed register that is to have multiple packed first format values, and wherein the functional unit is to convert multiple first format values from the second register.

12. The processor of claim 10, wherein an opcode portion of the instruction specifies which of multiple first format values from the second register to convert.

13. The processor of claim 10, wherein the first format value represents a part of pixel data.

14. The processor of claim 10, wherein the second register is a 128-bit register, wherein the first number of bits is 5 bits, and wherein the second number of bits is 8 bits.

15. The processor of claim 10, wherein the first format value is to be stored in a lower half portion of the second register.

16. The processor of claim 10, wherein the first format value is to be stored in a higher half portion of the second register.

17. The processor of claim 10, wherein the first format value is to have at least 3 sub-elements.

18. A processor comprising:

a first 128-bit register;

a decoder to decode an instruction;

a functional unit coupled with the decoder and the first 128-bit register to convert, responsive to the instruction, a first format value that is to be from a packed register of first format values and that is to represent a part of pixel data and that is to include at least three sub-elements to a second format value comprising a same number of sub-elements,

wherein the first format value sub-elements each are to have a first number of bits,

wherein each of the second format value sub-elements is to represent a number from a first format value sub-element with a second number of bits fewer than the first number of bits, and

wherein the functional unit is configured to store the second format value to an element in a lower half portion of the first 128-bit register.