Run-time parallelization of code execution based on an approximate register-access specification
First Claim
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1. A method, comprising:
- in a processor that processes instructions of program code, processing a first segment of the instructions;
constructing an approximate specification that defines register access by the instructions in the first segment by indicating for one or more destination registers that a respective number of writes in the first segment to each of the one or more destination registers exceeded a predefined threshold, without specifying the respective number;
making respective values of the one or more destination registers available to a second segment of the instructions only upon verifying that the values are known to be valid for readout by the second segment even though the approximate specification is not exact in pointing to the instructions that are last to write to the destination registers; and
processing the second segment at least partially in parallel with processing of the first segment, using the values made available from the first segment.
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Abstract
A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.
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Citations
27 Claims
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1. A method, comprising:
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in a processor that processes instructions of program code, processing a first segment of the instructions; constructing an approximate specification that defines register access by the instructions in the first segment by indicating for one or more destination registers that a respective number of writes in the first segment to each of the one or more destination registers exceeded a predefined threshold, without specifying the respective number; making respective values of the one or more destination registers available to a second segment of the instructions only upon verifying that the values are known to be valid for readout by the second segment even though the approximate specification is not exact in pointing to the instructions that are last to write to the destination registers; and processing the second segment at least partially in parallel with processing of the first segment, using the values made available from the first segment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A processor, comprising:
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an execution pipeline, which is configured to execute instructions of program code; and parallelization circuitry, which is configured to invoke a first hardware thread to process a first segment of the instructions, to construct an approximate specification that defines register access by the instructions by indicating for one or more destination registers that a respective number of writes in the first segment to each of the one or more destination registers exceeded a predefined threshold, without specifying the respective number, to make respective values of the one or more destination registers available to a second hardware thread, which processes a second segment of the instructions, only upon verifying that the values are known to be valid for readout by the second segment even though the approximate specification is not exact in pointing to the instructions that are last to write to the destination registers, so as to process the second segment by the second hardware thread at least partially in parallel with processing of the first segment using the respective values. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification