Context-based inspection for dark field inspection

• US 9,715,725 B2
• Filed: 12/08/2014
• Issued: 07/25/2017
• Est. Priority Date: 12/21/2013
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Luo, Tao, Zhang, Yong, Wu, Chaohong, Chen, Stephanie, Gao, Lisheng
• Primary Examiner(s): Roz, Mark
• Application Number:
  US14/563,845
• Publication Number:
  US 20150178907A1
• Time in Patent Office: 960 Days
• Field of Search: None
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/33 using feature-based methods

Abstract

Methods and systems for detecting defects on a wafer are provided. One method includes altering one or more design clips based on how the one or more design clips will appear in output generated by a wafer inspection process for a wafer. The method also includes aligning the one or more altered design clips to the output generated for the wafer during the wafer inspection process. In addition, the method includes detecting defects on the wafer based on the output aligned to the one or more altered design clips.

Claims

1. A computer-implemented method for detecting defects on a wafer, comprising:

altering one or more design clips for a current layer being inspected on the wafer based on how the one or more design clips printed on a wafer will appear in output generated by a wafer inspection process for the wafer;

aligning the one or more altered design clips to the output generated for the wafer during the wafer inspection process;

determining if one or more features in the output correspond to previous layer features on a layer of the wafer other than the current layer being inspected in the wafer inspection process by identifying portions of the output that appear to correspond to patterned features on the wafer that are not included in the one or more altered design clips as corresponding to the previous layer features and eliminating the one or more features corresponding to the previous layer features from the output prior to detecting defects on the wafer; and

detecting the defects on the wafer based on the output aligned to the one or more altered design clips, wherein said altering, aligning, and detecting are performed by one or more computer systems.

2. The method of claim 1, wherein the output generated for the wafer during the wafer inspection process is responsive to light scattered from the wafer.

3. The method of claim 1, wherein the one or more design clips correspond to only care areas on the wafer.

4. The method of claim 1, wherein said altering comprises determining how the one or more design clips printed on the wafer will appear in the output based on one or more parameters of the wafer inspection process.

5. The method of claim 1, wherein said altering comprises determining how the one or more design clips printed on the wafer will appear in the output based on a resolution of a wafer inspection system used for the wafer inspection process.

6. The method of claim 1, Wherein said altering comprises eliminating one or more features in the one or more design clips that will not appear in the output.

7. The method of claim 1, further comprising selecting one or more features in the one or more altered design clips that are used for said aligning.

8. The method of claim 1, wherein said altering comprises eliminating one or more features in the one or more design clips that will not be used for said aligning.

9. The method of claim 1, wherein the one or more altered design clips that are aligned to the output are not images acquired by a wafer inspection system.

10. The method of claim 1, wherein said altering is not performed during the wafer inspection process.

11. The method of claim 1, wherein said aligning and said detecting are performed for only one or more logic regions of the wafer.

12. The method of claim 1, wherein said aligning and said detecting are separately performed for each die inspected during the wafer inspection process.

13. The method of claim 1, wherein said aligning and said detecting are separately performed for each portion of the output generated for an area on the wafer in which a care area is located.

14. The method of claim 1, wherein the output aligned to the one or more altered design clips comprises a first portion of the output generated for a first die on the wafer, wherein said detecting comprises aligning second and third portions of the output generated for second and third dies on the wafer, respectively, to the first portion of the output and detecting the defects based on one or more comparisons of the first, second, and third portions of the output, and wherein the second and third dies are adjacent to the first die on the wafer.

15. The method of claim 1, wherein detecting the defects is performed for only the output aligned to the one or more altered design clips.

16. The method of claim 1, wherein results of said aligning are not used to align all dies in a swath of the output generated for the wafer during the wafer inspection process.

17. A non-transitory computer-readable medium storing program instructions executable on a computer system for performing computer-implemented method for detecting defects on a wafer, wherein the computer-implemented method comprises:

altering one or more design clips for a current layer being inspected on the wafer based on how the one or more design clips printed on a wafer will appear in output generated by a wafer inspection process for the wafer;

aligning the one or more altered design clips to the output generated for the wafer during the wafer inspection process;

determining if one or more features in the output correspond to previous layer features on a layer of the wafer other than the current layer being inspected in the wafer inspection process by identifying portions of the output that appear to correspond to patterned features on the wafer that are not included in the one or more altered design clips as corresponding to the previous layer features and eliminating the one or more features corresponding to the previous layer features from the output prior to detecting defects on the wafer; and

detecting the defects on the wafer based on the output aligned to the one or more altered design clips.

18. A system figured to detect defects on a wafer, comprising:

an optical inspection subsystem configured to generate output for a wafer; and

a computer subsystem configured for;

altering one or more design clips for a current layer being inspected on the wafer based on how the one or more design clips printed on the wafer will appear in the output generated by the optical inspection subsystem for the wafer;

aligning the one or more altered design clips to the output generated for the wafer by the optical inspection subsystem;

determining if one or more features in the output correspond to previous layer features on a layer of the wafer other than the current layer being inspected in the wafer inspection process by identifying portions of the output that appear to correspond to patterned features on the wafer that are not included in the one or more altered design clips as corresponding to the previous layer features and eliminating the one or more features corresponding to the previous layer features from the output prior to detecting defects on the wafer; and

detecting the defects on the wafer based on the output aligned to the one or more altered design clips.

19. The system of claim 18, wherein the output generated by the optical inspection subsystem for the wafer is responsive to light scattered from the wafer.

20. The system of claim 18, wherein the one or more design clips correspond to only care areas on the wafer.

21. The system of claim 18, wherein said altering comprises determining how the one or more design clips printed on the wafer will appear in the output based on one or more parameters of the optical inspection subsystem used to generate the output.

22. The system of claim 18, wherein said altering comprises determining how the one or more design clips printed on the wafer will appear in the output based on a resolution of the optical inspection subsystem.

23. The system of claim 18, wherein said altering comprises eliminating one or more features in the one or more design clips that will not appear in the output.

24. The system of claim 18, wherein the computer subsystem is further configured for selecting one or more features in the one or more altered design clips that are used for said aligning.

25. The system of claim 18, wherein said altering comprises eliminating one or more features in the one or more design clips that will not be used for said aligning.

26. The system of claim 18, wherein the one or more altered design clips that are aligned to the output are not images acquired by the optical inspection subsystem.

27. The system of claim 18, wherein said altering is not performed while the optical inspection subsystem is generating the output for the wafer.

28. The system of claim 18, wherein said aligning and said detecting are performed for only one or more logic regions of the wafer.

29. The system of claim 18, wherein said aligning and said detecting are separately performed for each die for which the output is generated by the optical inspection subsystem.

30. The system of claim 18, wherein said aligning and said detecting are separately performed for each portion of the output generated for an area on the wafer in which a care area is located.

31. The system of claim 18, wherein the output aligned to the one or more altered design clips comprises a first portion of the output generated for a first die on the wafer, wherein said detecting comprises aligning second and third portions of the output generated for second and third dies on the wafer, respectively, to the first portion of the output and detecting the defects based on one or more comparisons of the first, second, and third portions of the output, and wherein the second and third dies are adjacent to the first die on the wafer.

32. The system of claim 18, wherein detecting the defects is performed for only the output aligned to the one or more altered design clips.

33. The system of claim 18, wherein results of said aligning are not used to align all dies in a swath of the output generated for the wafer by the optical inspection subsystem.