Memory cells, memory cell arrays, methods of using and methods of making
First Claim
1. A semiconductor memory array comprising:
- a plurality of memory cells arranged in a matrix of at least one row and at least one column, wherein at least two of said memory cells each include;
a bipolar device comprising a floating body region; and
a non-volatile memory comprising a resistance change element;
wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said resistance change element, upon restoration of power to said memory cell.
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Accused Products
Abstract
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
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Citations
20 Claims
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1. A semiconductor memory array comprising:
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a plurality of memory cells arranged in a matrix of at least one row and at least one column, wherein at least two of said memory cells each include; a bipolar device comprising a floating body region; and a non-volatile memory comprising a resistance change element; wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said resistance change element, upon restoration of power to said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory array comprising:
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a plurality of memory cells arranged in a matrix of at least one row and at least two columns or at least two rows and at least one column, wherein at least two of said memory cells each include; a bipolar device comprising a floating body region; and a non-volatile memory comprising a resistance change element; wherein charge flow into said floating body region upon restoration of power to said memory cell depends on charge stored in said resistance change element. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification