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Memory cells, memory cell arrays, methods of using and methods of making

  • US 9,715,932 B2
  • Filed: 01/25/2017
  • Issued: 07/25/2017
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. A semiconductor memory array comprising:

  • a plurality of memory cells arranged in a matrix of at least one row and at least one column, wherein at least two of said memory cells each include;

    a bipolar device comprising a floating body region; and

    a non-volatile memory comprising a resistance change element;

    wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said resistance change element, upon restoration of power to said memory cell.

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