Wafer backside interconnect structure connected to TSVs

• US 9,716,074 B2
• Filed: 07/03/2014
• Issued: 07/25/2017
• Est. Priority Date: 09/22/2009
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Chiou, Wen-Chih, Shue, Shau-Lin
• Primary Examiner(s): Ho, Hoang-Quan
• Application Number:
  US14/323,617
• Publication Number:
  US 20140312494A1
• Time in Patent Office: 1,118 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/811 : the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8136 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a conductive via in the semiconductor substrate;

a first metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate and contacting the conductive via, wherein a surface of the first metal feature opposite the conductive via is substantially level with the back surface of the semiconductor substrate, wherein the conductive via is disposed between the first metal feature and the front surface of the semiconductor substrate in a plane, wherein the plane is perpendicular to the front surface of the semiconductor substrate;

a bump overlying and electrically connected to the first metal feature; and

a second metal feature formed between the first metal feature and the bump, wherein the second metal feature comprises a dual damascene structure.

2. The integrated circuit structure of claim 1, further comprising a dielectric layer on the back surface of the semiconductor substrate, wherein the second metal feature is disposed in the dielectric layer.

3. The integrated circuit structure of claim 1, wherein all horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the conductive via.

4. The integrated circuit structure of claim 1, wherein the first metal feature comprises:

a conductive barrier layer contacting the conductive via; and

a copper-containing metallic material over the conductive barrier layer.

5. The integrated circuit structure of claim 1 further comprising an active device at the front surface of the semiconductor substrate, and wherein the back surface is opposite the front surface of the semiconductor substrate.

6. The integrated circuit structure of claim 1, further comprising an additional metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein the additional metal feature does not extend through the semiconductor substrate.

16. The integrated circuit structure of claim 1 further comprising a redistribution line extending from the back surface of the semiconductor substrate into the semiconductor substrate.

17. The integrated circuit structure of claim 16 wherein lateral surfaces of the redistribution line and the first metal feature are substantially level.

18. The integrated circuit structure of claim 1, wherein a transistor is disposed at the front surface of the semiconductor substrate.

7. An integrated circuit structure comprising:

a semiconductor substrate;

an active device on a front surface of the semiconductor substrate;

a through-substrate via (TSV) extending at least partially through the semiconductor substrate;

a first metal feature at a back surface of the semiconductor substrate and electrically connected to the TSV, wherein all horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the TSV, and wherein the back surface is opposite the front surface of the semiconductor substrate, wherein a surface of the first metal feature opposite the TSV is substantially level with the back surface of the semiconductor substrate; and

a second metal feature on the back surface of the semiconductor substrate, wherein the second metal feature comprises a dual damascene structure.

8. The integrated circuit structure of claim 7, wherein the first metal feature extends from the back surface of the semiconductor substrate into the semiconductor substrate.

9. The integrated circuit structure of claim 7, further comprising a metal line in the semiconductor substrate.

10. The integrated circuit structure of claim 7, further comprising a bump electrically connected to the first metal feature.

11. The integrated circuit structure of claim 7, wherein the second metal feature contacts a top surface of the first metal feature.

12. The integrated circuit structure of claim 7, wherein the second metal feature is disposed in a dielectric layer, and wherein the integrated circuit structure further comprises an etch stop layer disposed between the semiconductor substrate and the dielectric layer.

13. An integrated circuit structure comprising:

a semiconductor substrate comprising an active device at a front surface of the semiconductor substrate;

an interconnect structure at the front surface of the semiconductor substrate;

a conductive via in the semiconductor substrate;

a first metal feature in the semiconductor substrate and electrically connected to the conductive via, wherein the first metal feature extends from a back surface of the semiconductor substrate into the semiconductor substrate, wherein the back surface is opposite the front surface of the semiconductor substrate;

a second metal feature adjacent the first metal feature extending from the back surface of the semiconductor substrate into the semiconductor substrate, wherein the second metal feature is a redistribution line, wherein the second metal feature is disposed outside of a region of the semiconductor substrate, wherein the region of the semiconductor substrate is bounded by a first line extending along a first sidewall of the conductive via and a second line extending along a second sidewall of the conductive via opposite the first sidewall, and wherein a portion of the semiconductor substrate is disposed between the first metal feature and the second metal feature; and

a third metal feature on the first metal feature, wherein the third metal feature comprises a dual damascene structure.

14. The integrated circuit structure of claim 13, wherein the conductive via extends at least partially through the interconnect structure.

15. The integrated circuit structure of claim 13 further comprising a bump on the first metal feature.