Semiconductor chip assembly and method for making same

• US 9,716,075 B2
• Filed: 09/11/2015
• Issued: 07/25/2017
• Est. Priority Date: 12/21/2010
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Kang, Teck-Gyu, Wang, Wei-Shun, Sato, Hiroaki, Hashimoto, Kiyoaki, Mohammed, Ilyas, Nakadaira, Yoshikuni, Masuda, Norihito, Damberg, Philip
• Primary Examiner(s): STONER, KILEY SHAWN
• Application Number:
  US14/851,925
• Publication Number:
  US 20160005711A1
• Time in Patent Office: 683 Days
• Field of Search: 2281791-18022, 438125, 438126
• CPC Class Codes: B23K 1/0016 Brazing of electronic components
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8138 Bonding interfaces outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/8185 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0195 : Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 3/341 : Surface mounted components
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Claims

1. A method for forming a microelectronic assembly comprising:

providing a substrate including a first dielectric layer having a first composition having electrically conductive elements thereon, the first dielectric layer having a coefficient of thermal expansion of at least 10 parts per million/°

C.;

forming a second dielectric layer overlying the first dielectric layer having a surface at which electrically conductive substrate contacts respectively overlying the conductive elements are exposed, the second dielectric layer having a Young'"'"'s modulus of less than about 2 GPa;

electrically connecting the conductive elements respectively with the substrate contacts by conductive vias extending through the second dielectric layer, the vias being disposed entirely below the respective substrate contacts; and

joining the substrate contacts to respective contacts exposed at a face of a microelectronic element, the surface of the substrate confronting the face of the microelectronic element,

wherein the microelectronic element further includes a dielectric region, in which the dielectric region includes a dielectric material having a low-k dielectric constant, and wherein a stiffness of the substrate contacts is such that the substrate contacts have a capability to move that limits an amount of stress transferred by the substrate contacts to the dielectric region of the microelectronic element by said movement of the substrate contacts to below a level of stress that would be transferred to the dielectric region of the microelectronic element, such as caused by differential expansion or contraction absent said movement of the substrate contacts, in which the amount of stress is lower than a tolerance level of stress of the dielectric region.

2. The method of claim 1, wherein a ratio of a diameter of the conductive vias to a diameter of the respective substrate contacts is less than 40%.

3. The method of claim 1, wherein the vias extend through the second dielectric layer from substantially a center of a surface of the respective substrate contacts confronting the vias.

4. The method of claim 1, wherein the vias have a thickness extending in a direction perpendicular to the surface of the second dielectric layer of at least 20 microns.

5. The method of claim 4, wherein a ratio of a diameter of the substrate contacts to a diameter of the conductive vias is less than 40%.

6. The method of claim 1, wherein the first dielectric layer and the microelectronic element have a Young'"'"'s modulus exceeding the Young'"'"'s modulus of the second dielectric layer.

7. The method of claim 1, wherein the substrate contacts have a thickness extending in a direction perpendicular to the surface of the second dielectric layer of less than 20 microns.

8. The method of claim 1, wherein the substrate contacts, the vias and the second dielectric layer are adapted to permit displacement of the substrate contacts relative to the conductive elements, wherein the displacement appreciably relieves mechanical stresses, such as caused by differential thermal expansion or contraction which would be present in electrical connections between the substrate contacts and the microelectronic element absent such displacement.

9. The method of claim 1 further comprising:

joining the contacts of the substrate and the microelectronic elements through a bond metal including at least one of solder, tin or indium.

10. The method of claim 1, wherein the coefficient of thermal expansion of the first dielectric layer is greater than a coefficient of thermal expansion of the microelectronic element, such that the microelectronic element applies substantial loads to the substrate contacts due to a difference in the coefficients of thermal expansion between the first dielectric layer and the microelectronic element.

11. The method of claim 1, wherein the first dielectric layer and the microelectronic element have a Young'"'"'s modulus exceeding the Young'"'"'s modulus of the second dielectric layer, and wherein the coefficient of thermal expansion of the first dielectric layer is greater than a coefficient of thermal expansion of the microelectronic element.