Three-dimensional memory device with different thickness insulating layers and method of making thereof

• US 9,716,105 B1
• Filed: 08/02/2016
• Issued: 07/25/2017
• Est. Priority Date: 08/02/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Tsutsumi, Masanori
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/226,132
• Time in Patent Office: 357 Days
• Field of Search: 257314, 257324, 257326, 257E2169, 257E21614
• CPC Class Codes: H01L 21/02326 into a nitride layer, e.g. changing SiN to SiON
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures including a memory film and a vertical semiconductor channel and extending through a first region of the alternating stack, and support pillar structures extending through a second region of the alternating stack that is laterally offset from the first region. Each insulating layer includes a respective first insulating material portion having a respective first insulator thickness in the first region of the alternating stack and a respective second insulating material portion having a respective second insulator thickness that is greater than the respective first insulator thickness in the second region.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

memory stack structures extending through a first region of the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and

support pillar structures extending through a second region of the alternating stack that is laterally offset from the first region,

wherein each insulating layer includes a respective first insulating material portion having a respective first insulator thickness in the first region of the alternating stack and a respective second insulating material portion having a respective second insulator thickness that is greater than the respective first insulator thickness in the second region.

2. The three-dimensional memory device of claim 1, wherein each electrically conductive layer that is not the topmost layer or the bottommost layer of the alternating stack has a respective first conductor thickness in the first region of the alternating stack and a respective second conductor thickness that is less than the respective first conductor thickness in the second region of the alternating stack.

3. The three-dimensional memory device of claim 2, wherein a difference between the first insulator thickness and the second insulator thickness is the same as a difference between the first conductor thickness and the second conductor thickness.

4. The three-dimensional memory device of claim 1, wherein each second insulating material portion of the insulating layers includes a first silicon oxide material portion, an upper second silicon oxide material portion overlying the first silicon oxide material portion, and a lower second silicon oxide material portion underlying the first silicon oxide material portion in the second region.

5. The three-dimensional memory device of claim 1, wherein:

the first silicon oxide material portion includes a first silicon oxide material; and

the upper second silicon oxide material portion and the lower second silicon oxide material portion include a second silicon oxide material that is different from the first silicon oxide material in at least one of composition and structure.

6. The three-dimensional memory device of claim 5, wherein the second silicon oxide material has a lower etch rate than the first silicon oxide material in a hot phosphoric acid solution including phosphoric acid at a concentration in a range from 80% to 94%.

7. The three-dimensional memory device of claim 6, wherein each of the upper second silicon oxide material portion, the lower second silicon oxide material portion, and the first silicon oxide material portion physically contacts an element selected from a backside blocking dielectric layer and the electrically conductive layers within the alternating stack.

8. The three-dimensional memory device of claim 1, further comprising a thickness transition region located between the first region and the second region,

wherein:

each of the insulating layers has a gradually varying thickness between the first region and the second region; and

each of the electrically conductive layers has a gradually varying thickness between the first region and the second region.

9. The three-dimensional memory device of claim 1, wherein the second region comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack, wherein the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack.

10. The three-dimensional memory device of claim 1, wherein the support pillar structures comprise respective dielectric material portions contacting the substrate and laterally surrounded by at least one electrically conductive layer within the alternating stack.

11. The three-dimensional memory device of claim 1, further comprising:

a backside trench extending through the alternating stack;

an insulating spacer located at a periphery of the backside trench;

a source region located in an upper portion of the substrate and underlying the backside trench; and

a backside contact via structure contacting the source region and laterally surrounded by the insulating spacer.

12. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.