Semiconductor devices with enhanced deterministic doping and related methods

• US 9,716,147 B2
• Filed: 06/09/2015
• Issued: 07/25/2017
• Est. Priority Date: 06/09/2014
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert J.
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US14/734,412
• Publication Number:
  US 20150357414A1
• Time in Patent Office: 777 Days
• Field of Search: 438478
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

Claims

1. A method for making a semiconductor device comprising:

forming a plurality of stacked groups of layers on a semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region; and

performing a rapid thermal anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

2. The method of claim 1 wherein selectively implanting comprises using a focused ion beam.

3. The method of claim 2 further comprising selecting a depth of the focused ion beam to a depth of the plurality of stacked groups of layers.

4. The method of claim 1 wherein the at least one localized region comprises a plurality thereof.

5. The method of claim 1 wherein the dopant has a fall-off in a range of 3.0 to 3.3 nm/decade.

6. The method of claim 1 wherein forming the plurality of stacked groups of layers comprises forming laterally-spaced apart stacked groups of layers on the semiconductor substrate;

and wherein implanting comprises implanting the dopant in respective localized regions beneath each of the laterally-spaced apart stacked groups of layers.

7. The method of claim 1 wherein the dopant comprises at least one of boron and arsenic.

8. The method of claim 1 wherein each base semiconductor portion comprises silicon.

9. The method of claim 1 wherein each base semiconductor portion comprises germanium.

10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

11. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

12. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

13. A method for making a semiconductor device comprising:

forming a plurality of stacked groups of layers on a semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region; and

performing a rapid thermal anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region with the dopant being isolated from the plurality of stacked groups of layers by portions of the semiconductor substrate therebetween.

14. The method of claim 13 wherein selectively implanting comprises using a focused ion beam.

15. The method of claim 14 further comprising selecting a depth of the focused ion beam to a depth of the plurality of stacked groups of layers.

16. The method of claim 13 wherein the at least one localized region comprises a plurality thereof.

17. The method of claim 13 wherein the dopant has a fall-off in a range of 3.0 to 3.3 nm/decade.

18. The method of claim 13 wherein forming the plurality of stacked groups of layers comprises forming laterally-spaced apart stacked groups of layers on the semiconductor substrate;

and wherein implanting comprises implanting the dopant in respective localized regions beneath each of the laterally-spaced apart stacked groups of layers.

19. The method of claim 13 wherein the dopant comprises at least one of boron and arsenic.

20. The method of claim 13 wherein each base semiconductor portion comprises silicon.

21. The method of claim 13 wherein each base semiconductor portion comprises germanium.