Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

• US 9,716,153 B2
• Filed: 07/01/2012
• Issued: 07/25/2017
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jenne, Fredrick, Levy, Sagy, Ramkumar, Krishnaswamy
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US13/539,459
• Publication Number:
  US 20130306975A1
• Time in Patent Office: 1,850 Days
• Field of Search: 257225, 257296, 257298, 257300, 257314, 257390, 257E27084, 257E27085, 257E27098, 257E29309, 257E21209, 257E21613, 257E21645, 257E21662, 257E21679, 257315, 257324
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

Claims

1. A charge trap memory device, comprising:

a layer of semiconducting material on an insulating layer on a surface of a substrate;

a source region, a drain region, and a channel region electrically connecting the source region and drain region formed in the layer of semiconducting material, wherein the insulating layer separates the channel from the substrate;

a tunnel dielectric layer disposed above the substrate over the channel region; and

a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer, and a second deuterated layer disposed above the second nitride layer,

wherein the second nitride layer comprises a, deuterium-free trap-dense, oxygen-lean nitride layer and includes a majority of charge traps distributed in the multi-layer charge-trapping region, and the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.

2. The memory device of claim 1, wherein the first nitride layer is deuterated, and wherein a concentration of deuterium in the first nitride layer is less than a concentration of deuterium in the first deuterated layer.

3. The memory device of claim 2, wherein there is a gradient of deuterium atom concentration from a high concentration of deuterium in the first deuterated layer to a low concentration of deuterium in the first nitride layer.

4. The memory device of claim 1, wherein the channel region comprises recrystallized polysilicon.

5. The memory device of claim 1, wherein the multi-layer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

6. The memory device of claim 1, wherein the channel region comprises polysilicon.

7. The memory device of claim 1, wherein the first nitride layer and the second nitride layer comprise silicon nitride formed using dichlorosilane.

8. A charge trap memory device, comprising:

a layer of semiconducting material overlying a surface of a substrate;

a source region, a drain region, and a channel region electrically connecting the source region and drain region formed in the layer of semiconducting material;

a tunnel dielectric layer disposed on the substrate over the channel region;

a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer, and a second deuterated layer disposed above the second nitride layer;

a blocking dielectric layer disposed on the second deuterated layer, the second deuterated layer separating the second nitride layer from the blocking dielectric layer; and

a gate layer disposed on the blocking dielectric layer,

wherein the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.

9. The memory device of claim 8, wherein the second nitride layer comprises a deuterium-free trap-dense, oxygen-lean nitride layer and includes a majority of charge traps distributed in the multi-layer charge-trapping region.

10. The memory device of claim 8, wherein the multi-layer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

11. The memory device of claim 8, wherein the layer of semiconducting material is formed on an insulating layer on the surface of the substrate separating the channel from the substrate.

12. A charge trap memory device, comprising:

a layer of semiconducting material overlying a surface of a substrate;

a source region, a drain region, and a channel region electrically connecting the source region and drain region formed in the layer of semiconducting material;

a tunnel dielectric layer disposed above the substrate over the channel region; and

a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer, and a second deuterated layer disposed above the second nitride layer,

wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer, and wherein first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.

13. The memory device of claim 12, wherein the second nitride layer comprises a trap-dense, oxygen-lean nitride layer and includes a majority of charge traps distributed in the multi-layer charge-trapping region.

14. The memory device of claim 12, wherein the multi-layer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

15. The memory device of claim 12, wherein the first nitride layer is deuterated, and wherein a concentration of deuterium in the first nitride layer is less than a concentration of deuterium in the first deuterated layer.

16. The memory device of claim 15, wherein there is a gradient of deuterium atom concentration from a high concentration of deuterium in the first deuterated layer to a low concentration of deuterium in the first nitride layer.

17. The memory device of claim 12, wherein the channel region comprises recrystallized polysilicon.