Gate structure having designed profile and method for forming the same

• US 9,716,161 B2
• Filed: 10/01/2014
• Issued: 07/25/2017
• Est. Priority Date: 10/01/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Kai-Li, Chang, Che-Cheng
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US14/503,994
• Publication Number:
  US 20160099337A1
• Time in Patent Office: 1,028 Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C.

Claims

1. A method for forming a semiconductor structure, comprising:

forming a polysilicon layer over a substrate;

forming a hard mask structure over the polysilicon layer;

etching the polysilicon layer to form a dummy gate structure below the hard mask structure;

forming spacers over sidewalls of the dummy gate structure; and

replacing the dummy gate structure by a metal gate structure,

wherein the dummy gate structure has a top width, a neck width, and a bottom width, and the neck width is larger than both the top width and the bottom width.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the step of etching the polysilicon layer to form the dummy gate structure further comprises:

etching the polysilicon layer to form an upper portion of the dummy gate structure by a first etching process; and

etching the polysilicon layer to form a bottom portion of the dummy gate structure by a second etching process,

wherein a first etching gas and a second gas are used in both the first etching process and the second etching process, and a volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than a volume ratio of the first etching gas to the second etching gas used in the second etching process.

3. The method for forming a semiconductor structure as claimed in claim 2, wherein the first etching gas is CF₄, and the second etching gas is Cl₂.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein a ratio of the neck width to the top width is in a range from about 1.01 to about 1.51.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein a ratio of the neck width to the bottom width is in a range from about 1.01 to about 1.44.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein the top width is a width of a top surface of the dummy gate structure, the bottom width is a width of a bottom surface of the dummy gate structure, and the neck width is the largest width of the dummy gate structure measured from a position located between the top surface and the bottom surface of the dummy gate structure.

7. The method for forming a semiconductor structure as claimed in claim 6, wherein a first distance is measured from the top surface to the bottom surface of the dummy gate structure, a second distance is measured from the bottom surface of the dummy gate structure to the position from which the neck width is measured, and a ratio of the second distance to the first distance is in a range from about 0.26 to about 0.39.

8. The method for forming a semiconductor structure as claimed in claim 1, wherein the metal gate structure has a top surface, a bottom surface, and a curved sidewall, and an angle between the top surface and the curved sidewall and an angle between the bottom surface and the curved sidewall are both larger than 90°

.

9. A method for forming a semiconductor structure, comprising:

forming a dummy gate layer over a substrate;

patterning a top portion of the dummy gate layer to form an upper portion of a dummy gate structure by performing a first etching process; and

patterning a bottom portion of the dummy gate layer to form a bottom portion of the dummy gate structure by performing a second etching process,

wherein the first etching process is different from the second etching process, such that a first inclination of a sidewall of the upper portion is different from a second inclination of a sidewall of the bottom portion.

10. The method for forming a semiconductor structure as claimed in claim 9, wherein both the first etching process and the second etching process comprise using a first etching gas and a second etching gas, but a volume ratio of the first etching gas to the second etching gas used in the first etching process is different from a volume ratio of the first etching gas to the second etching gas used in the second etching process.

11. The method for forming a semiconductor structure as claimed in claim 10, wherein the first etching gas comprises CF₄, CH₂F₂, or CHF₃, and the second etching gas comprises Cl₂, HBr, or SF₆.

12. The method for forming a semiconductor structure as claimed in claim 11, further comprising:

replacing the dummy gate structure by a metal gate structure,

wherein the metal gate structure has curved sidewalls.

13. The method for forming a semiconductor structure as claimed in claim 10, wherein the volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than the volume ratio of the first etching gas to the second etching gas used in the second etching process, such that the first inclination of the sidewall of the upper portion is smaller than the second inclination of the sidewall of the bottom portion.

14. The method for forming a semiconductor structure as claimed in claim 13, wherein the upper portion of the dummy gate structure has a first height, and the bottom portion of the dummy gate structure has a second height, and a ratio of the first height to the second height is in a range from about 1.5 to about 3.

15. The method for forming a semiconductor structure as claimed in claim 9, wherein an angle between the first inclination and the second inclination measured from an inner side of the dummy gate structure is smaller than 180°

.

16. A method for forming a semiconductor structure, comprising:

forming a dummy gate layer over a substrate;

patterning the dummy gate layer to form a dummy gate structure having an upper portion and a bottom portion such that a first inclination of a sidewall of the upper portion of the dummy gate structure is smaller than a second inclination of a sidewall of the bottom portion of the dummy gate structure; and

replacing the dummy gate structure by a metal gate structure,

wherein an angle between the first inclination and the second inclination measured from an inner side of the dummy gate structure is smaller than 180°

.

17. The method for forming a semiconductor structure as claimed in claim 16, wherein the upper portion of the dummy gate structure is formed by performing a first etching process and the bottom portion of the dummy gate structure is formed by performing a second etching process, the first etching process is different from the second etching process.

18. The method for forming a semiconductor structure as claimed in claim 17, wherein both the first etching process and the second etching process comprise using a first etching gas and a second etching gas, but a volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than a volume ratio of the first etching gas to the second etching gas used in the second etching process.

19. The method for forming a semiconductor structure as claimed in claim 16, wherein the dummy gate structure has a top width at its top surface, a bottom width at its bottom surface, and a neck width at a middle of the dummy gate structure, and the neck width is larger than the top width and the bottom width.

20. The method for forming a semiconductor structure as claimed in claim 16, wherein the dummy gate layer is a polysilicon layer.